ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_ethosu_shim.h File Reference

Arm ethos-u-core-driver C API shim over the ra8_npu driver (RA8P1-only). More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_device.h"
Include dependency graph for ra8_ethosu_shim.h:

Go to the source code of this file.

Detailed Description

Arm ethos-u-core-driver C API shim over the ra8_npu driver (RA8P1-only).

Tag
[Ring 3 / HAL] {World: S}

This is the ADAPTER that lets the vendored TensorFlow Lite for Microcontrollers (TFLite-micro) Ethos-U operator kernel drive the RA8P1's Arm Ethos-U55 NPU through this project's first-party ra8_npu HAL, instead of the upstream Arm ethos-u-core-driver library (which is NOT vendored in this tree). It re-implements the MINIMAL slice of the Arm driver C API that the kernel calls – three functions – on top of ra8_npu_init() / ra8_npu_submit() / ra8_npu_run() / ra8_npu_wait():

  • ::ethosu_reserve_driver – lazily bring the single NPU up and hand back a persistent driver handle.
  • ::ethosu_invoke_v3 – translate a (command stream + base-pointer array) call into an ra8_npu_job_t and run it.
  • ::ethosu_release_driver – a no-op: the one NPU stays initialised.

The signatures here are transcribed byte-for-byte from the Arm ethosu_driver.h public prototypes (SPDX Apache-2.0, reference-only) so this shim is a drop-in symbol provider: if the real TFLite-micro Ethos-U kernel (which #includes the Arm header and calls these symbols) is ever linked, it resolves against this shim with no source change. The names deliberately do NOT carry this project's ra8_ / k_ prefixes – they are an external ABI contract owned by Arm, and renaming them would defeat the drop-in purpose.

Status / gating

RA8P1-only: the whole surface is guarded behind RA8_HAS_NPU (defined only for -DRA8_DEVICE_RA8P1, see ra8_device.h), exactly like ra8_npu.h. There is no RA8P1 board yet, so the adapter is host-tested for the exact NPU register-programming contract only (see tests/misc/src/test_ra8_ethosu_shim.c); a real Vela-compiled inference on silicon is a follow-up on the RA8P1 NPU epic. This shim intentionally does NOT enable the dormant TFLite-micro C++ stack (RA8_USE_TFLITE_MICRO, OFF by default): it only PROVIDES the symbols that stack would need.

Threading

Not thread-safe. The NPU is a single-job engine and the shim keeps one static driver context; the caller owns serialisation, the same contract as ra8_npu.

Since
0.1.0

Definition in file ra8_ethosu_shim.h.