ra8_device.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
/* -------------------------------------------------------------------------- */
/* Device selection */
/* -------------------------------------------------------------------------- */
 
/*
 * Exactly one device must be selected. Default to RA8D2 when the compile
 * command names neither, so pre-existing RA8D2 firmware builds and the
 * host unit-test build (which pass no -DRA8_DEVICE_* flag) keep the RA8D2
 * behaviour they have today, with zero source churn.
 */
#if !defined(RA8_DEVICE_RA8D2) && !defined(RA8_DEVICE_RA8P1)
#define RA8_DEVICE_RA8D2 (1)
#endif
 
#if defined(RA8_DEVICE_RA8D2) && defined(RA8_DEVICE_RA8P1)
#error "ra8_device.h: define at most one of RA8_DEVICE_RA8D2 / RA8_DEVICE_RA8P1"
#endif

typedef enum : uint16_t {
  k_ra8_device_ra8d2 = 0x8D2U, 
  k_ra8_device_ra8p1 = 0x8F1U, 
#ifdef RA8_DEVICE_RA8P1
  k_ra8_device_current = k_ra8_device_ra8p1 
#else
  k_ra8_device_current = k_ra8_device_ra8d2 
#endif
} ra8_device_id_t;
 
/* -------------------------------------------------------------------------- */
/* Feature-presence flags */
/* -------------------------------------------------------------------------- */
 
/*
 * Build-configuration flags (an explicitly-allowed macro use: they gate
 * conditional compilation, not integer arithmetic). Prefer these semantic
 * names over `#if defined(RA8_DEVICE_RA8P1)` in feature-guarded code so the
 * intent ("this chip has an NPU") survives the arrival of a future part.
 *
 * The delta set below is the COMPLETE list of hardware differences found from
 * primary sources; every other peripheral, base address, and memory region is
 * identical across the two parts.
 *
 * NOTE (issue #224): an earlier draft of this delta set listed a "legacy
 * ETHERC/EDMAC MAC at 0x40354000" as an RA8P1-only addition. That was a misread
 * and is deliberately absent here. The RA8P1 Hardware User's Manual
 * (R01UH1064EJ0130) and datasheet (R01DS0439EJ0130) contain no ETHERC block,
 * none of the classic ETHERC/EDMAC registers (ECMR / EDMR / ...), and nothing
 * based at 0x40354000 (that window is USBHS 0x40351000 / SCI 0x40358000 /
 * SPI 0x4035C000). The token "EDMAC" appears only in the Buses chapter, where
 * BOTH manuals state verbatim that "EDMAC ... means the GWCA function of ESWM"
 * -- the descriptor-DMA bus initiator of the shared R-Switch, which the RA8D2
 * has too. The RA8P1's only Ethernet is the same R-Switch / ESWM subsystem as
 * the RA8D2 (identical HUM chapters 30-36 and register bases), so there is no
 * ETHERC feature flag. Do not re-add one without a primary-source register map.
 *
 * NOTE (issue #516): an earlier draft also listed "OFS3 / WDT1 option register"
 * as RA8D2-only, behind an `RA8_HAS_OFS3` flag. That was a misread of Renesas
 * FSP metadata and is deliberately absent here. BOTH parts have OFS3: RA8P1 HUM
 * R01UH1064EJ0130 Ch 7.2.6 "OFS3, OFS3_SEC : Option Function Select Register 3"
 * p 288 and Ch 7.2.7 "OFS3_SEL ... for Security" p 290 document the same word,
 * at the same addresses and with the same WDT1 bit fields, as RA8D2 HUM
 * R01UH1065EJ0130 Ch 7.2.6 p 287 / Ch 7.2.7 p 289. The RA8P1 likewise has the
 * WDT1 that OFS3 configures (datasheet R01DS0439EJ0130: "Watchdog Timer (WDT)
 * x 2"; WDT1 at 0x4020_2600). FSP's `BSP_FEATURE_BSP_HAS_OFS3` is 0 for ra8p1,
 * which contradicts Renesas' own manual and has no consumer in open FSP source;
 * it is not evidence. Do not re-add an OFS3 feature flag.
 */
#ifdef RA8_DEVICE_RA8P1
#define RA8_HAS_NPU                                                                                \
  (1) 
#define RA8_HAS_NPUCLK (1) 
#else
/* RA8_HAS_NPU / RA8_HAS_NPUCLK intentionally undefined (NPU is RA8P1-only). */
#endif

typedef enum : uint8_t {
#ifdef RA8_DEVICE_RA8P1
  k_ra8_feat_npu    = 1U, 
  k_ra8_feat_npuclk = 1U, 
#else
  k_ra8_feat_npu    = 0U, 
  k_ra8_feat_npuclk = 0U, 
#endif 
} ra8_device_feature_t;
 
/* -------------------------------------------------------------------------- */
/* Memory map */
/* -------------------------------------------------------------------------- */

typedef enum : uintptr_t {
  k_ra8_mem_mram_base     = 0x02000000U, 
  k_ra8_mem_itcm_base     = 0x00000000U, 
  k_ra8_mem_dtcm_base     = 0x20000000U, 
  k_ra8_mem_sram_base     = 0x22000000U, 
  k_ra8_mem_sdram_base    = 0x68000000U, 
  k_ra8_mem_ospi_cs0_base = 0x80000000U, 
  k_ra8_mem_ospi_cs1_base = 0x90000000U, 
} ra8_device_mem_base_t;

typedef enum : uint32_t {
  k_ra8_mem_mram_size = 0x00100000U, 
  k_ra8_mem_sram_size = 0x001A0000U, 
  k_ra8_mem_itcm_size = 0x00010000U, 
  k_ra8_mem_dtcm_size = 0x00010000U, 
} ra8_device_mem_size_t;
 
#ifdef __cplusplus
}
#endif