Reset block register layout (offsets, bit masks, accessors)for the Renesas RA8D2. More...

#include <stdint.h>

Include dependency graph for ra8_reset_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_reset_addr_t : uintptr_t { k_ra8_reset_sysc_base_addr = 0x4001E000UL , k_ra8_reset_scb_aircr_addr = 0xE000ED0CUL }
	Memory-mapped base addresses used by the reset driver. More...
enum	ra8_reset_offset_t : uint16_t { k_ra8_reset_off_rstsr1 = 0x0C0U , k_ra8_reset_off_prcr = 0x3FAU , k_ra8_reset_off_rstsar = 0x3C4U , k_ra8_reset_off_rstsr0 = 0xA40U , k_ra8_reset_off_rstsr2 = 0xA44U , k_ra8_reset_off_rstsr3 = 0xA48U , k_ra8_reset_off_syrstmsk0 = 0xAD0U , k_ra8_reset_off_syrstmsk1 = 0xAD4U , k_ra8_reset_off_syrstmsk2 = 0xAD8U , k_ra8_reset_off_temprcr = 0xADCU , k_ra8_reset_off_temprlr = 0xAE0U }
	Offset (within SYSC) of every register the reset driver touches. More...
enum	ra8_reset_prcr_bits_t : uint16_t { k_ra8_reset_prcr_key = 0xA500U , k_ra8_reset_prcr_prc5_msk = 0x0020U , k_ra8_reset_prcr_pr_bits_msk = 0x00FFU }
	PRCR (Protect Register) password + PRC5 enable bit. More...
enum	ra8_reset_syrstmsk0_bits_t : uint8_t { k_ra8_reset_syrstmsk0_iwdt_msk = 0x01U , k_ra8_reset_syrstmsk0_wdt0_msk = 0x02U , k_ra8_reset_syrstmsk0_sw_msk = 0x04U , k_ra8_reset_syrstmsk0_clu0_msk = 0x10U , k_ra8_reset_syrstmsk0_lm0_msk = 0x20U , k_ra8_reset_syrstmsk0_cm_msk = 0x40U , k_ra8_reset_syrstmsk0_bus_msk = 0x80U }
	SYRSTMSK0 mask bits (1 = reset disabled). More...
enum	ra8_reset_syrstmsk1_bits_t : uint8_t { k_ra8_reset_syrstmsk1_wdt1_msk = 0x02U , k_ra8_reset_syrstmsk1_clu1_msk = 0x10U , k_ra8_reset_syrstmsk1_lm1_msk = 0x20U }
	SYRSTMSK1 mask bits (1 = reset disabled). More...
enum	ra8_reset_syrstmsk2_bits_t : uint8_t { k_ra8_reset_syrstmsk2_pvd1_msk = 0x01U , k_ra8_reset_syrstmsk2_pvd2_msk = 0x02U }
	SYRSTMSK2 mask bits (1 = reset disabled). More...
enum	ra8_reset_temprcr_bits_t : uint8_t { k_ra8_reset_temprcr_tempren_msk = 0x01U , k_ra8_reset_temprcr_tsnen_msk = 0x02U , k_ra8_reset_temprcr_cmpen_msk = 0x04U , k_ra8_reset_temprcr_tsnkeep_msk = 0x08U }
	TEMPRCR (Temperature Monitor Reset Control) bits. More...
enum	ra8_reset_temprlr_bits_t : uint8_t { k_ra8_reset_temprlr_lock_msk = 0x01U }
	TEMPRLR (Temperature Monitor Reset Lock) bits. More...
enum	ra8_rstsr0_bits_t : uint8_t { k_ra8_reset_rstsr0_porf_pos = 0U , k_ra8_reset_rstsr0_lvd0rf_pos = 1U , k_ra8_reset_rstsr0_lvd1rf_pos = 2U , k_ra8_reset_rstsr0_lvd2rf_pos = 3U , k_ra8_reset_rstsr0_lvd4rf_pos = 5U , k_ra8_reset_rstsr0_lvd5rf_pos = 6U , k_ra8_reset_rstsr0_dpsrstf_pos = 7U , k_ra8_reset_rstsr0_porf_msk = 0x01U , k_ra8_reset_rstsr0_lvd0rf_msk = 0x02U , k_ra8_reset_rstsr0_lvd1rf_msk = 0x04U , k_ra8_reset_rstsr0_lvd2rf_msk = 0x08U , k_ra8_reset_rstsr0_lvd4rf_msk = 0x20U , k_ra8_reset_rstsr0_lvd5rf_msk = 0x40U , k_ra8_reset_rstsr0_dpsrstf_msk = 0x80U }
	RSTSR0 bit positions / masks. More...
enum	ra8_rstsr1_bits_t : uint32_t { k_ra8_reset_rstsr1_iwdtrf_pos = 0U , k_ra8_reset_rstsr1_wdtrf_pos = 1U , k_ra8_reset_rstsr1_swrf_pos = 2U , k_ra8_reset_rstsr1_clurf_pos = 4U , k_ra8_reset_rstsr1_lm0rf_pos = 5U , k_ra8_reset_rstsr1_bussrf_pos = 10U , k_ra8_reset_rstsr1_cmrf_pos = 14U , k_ra8_reset_rstsr1_wdt1rf_pos = 17U , k_ra8_reset_rstsr1_clu1rf_pos = 20U , k_ra8_reset_rstsr1_lm1rf_pos = 21U , k_ra8_reset_rstsr1_nwrf_pos = 22U , k_ra8_reset_rstsr1_iwdtrf_msk = 0x00000001UL , k_ra8_reset_rstsr1_wdtrf_msk = 0x00000002UL , k_ra8_reset_rstsr1_swrf_msk = 0x00000004UL , k_ra8_reset_rstsr1_clurf_msk = 0x00000010UL , k_ra8_reset_rstsr1_lm0rf_msk = 0x00000020UL , k_ra8_reset_rstsr1_bussrf_msk = 0x00000400UL , k_ra8_reset_rstsr1_cmrf_msk = 0x00004000UL , k_ra8_reset_rstsr1_wdt1rf_msk = 0x00020000UL , k_ra8_reset_rstsr1_clu1rf_msk = 0x00100000UL , k_ra8_reset_rstsr1_lm1rf_msk = 0x00200000UL , k_ra8_reset_rstsr1_nwrf_msk = 0x00400000UL }
	RSTSR1 bit positions and masks. More...
enum	ra8_rstsr2_bits_t : uint8_t { k_ra8_reset_rstsr2_cwsf_pos = 0U , k_ra8_reset_rstsr2_cwsf_msk = 0x01U }
	RSTSR2 bit positions / masks (per HUM Ch 6.2.4 p 261). More...
enum	ra8_rstsr3_bits_t : uint8_t { k_ra8_reset_rstsr3_cvmrf_pos = 0U , k_ra8_reset_rstsr3_ocprf_pos = 4U , k_ra8_reset_rstsr3_temprf_pos = 7U , k_ra8_reset_rstsr3_cvmrf_msk = 0x01U , k_ra8_reset_rstsr3_ocprf_msk = 0x10U , k_ra8_reset_rstsr3_temprf_msk = 0x80U }
	RSTSR3 bit positions / masks (per HUM Ch 6.2.5 p 261-262). More...
enum	ra8_rstsar_bits_t : uint32_t { k_ra8_reset_rstsar_nonsec0_pos = 0U , k_ra8_reset_rstsar_nonsec1_pos = 1U , k_ra8_reset_rstsar_nonsec2_pos = 2U , k_ra8_reset_rstsar_nonsec3_pos = 3U , k_ra8_reset_rstsar_nonsec4_pos = 4U , k_ra8_reset_rstsar_field_msk = 0x0000001FUL }
	RSTSAR bit positions / masks (per HUM Ch 6.2.1 p 256). More...
enum	ra8_reset_aircr_t : uint32_t { k_ra8_reset_aircr_vectkey_pos = 16U , k_ra8_reset_aircr_vectkey_value = 0x05FAUL , k_ra8_reset_aircr_sysresetreq_pos = 2U , k_ra8_reset_aircr_sysresetreq_msk = 0x00000004UL }
	AIRCR fields touched when triggering a software reset. More...

Functions
static volatile uint8_t *	ra8_reset_rstsr0 (void)
	Pointer to the 8-bit RSTSR0 register.
static volatile uint32_t *	ra8_reset_rstsr1 (void)
	Pointer to the 32-bit RSTSR1 register.
static volatile uint8_t *	ra8_reset_rstsr2 (void)
	Pointer to the 8-bit RSTSR2 register.
static volatile uint8_t *	ra8_reset_rstsr3 (void)
	Pointer to the 8-bit RSTSR3 register.
static volatile uint32_t *	ra8_reset_rstsar (void)
	Pointer to the 32-bit RSTSAR (security attribution) register.
static volatile uint32_t *	ra8_reset_aircr (void)
	Pointer to the Cortex-M85 SCB AIRCR register.
static volatile uint16_t *	ra8_reset_prcr (void)
	Pointer to the 16-bit PRCR write-protect register.
static volatile uint8_t *	ra8_reset_syrstmsk0 (void)
	Pointer to the 8-bit SYRSTMSK0 register.
static volatile uint8_t *	ra8_reset_syrstmsk1 (void)
	Pointer to the 8-bit SYRSTMSK1 register.
static volatile uint8_t *	ra8_reset_syrstmsk2 (void)
	Pointer to the 8-bit SYRSTMSK2 register.
static volatile uint8_t *	ra8_reset_temprcr (void)
	Pointer to the 8-bit TEMPRCR register.
static volatile uint8_t *	ra8_reset_temprlr (void)
	Pointer to the 8-bit TEMPRLR register.

Detailed Description

Reset block register layout (offsets, bit masks, accessors)

for the Renesas RA8D2.

The RA8D2 reset-cause / reset-control registers physically live inside the System Control (SYSC) block at base 0x4001_E000. The shared header ra8_system_regs.h already exposes a partial map of SYSC and includes pointer accessors for RSTSR0, RSTSR1 and RSTSR2. The shared brief explicitly forbids editing the shared system header from a per-driver task, so this header mirrors the subset of reset registers needed by ra8_reset.c (the three RSTSR flags plus RSTSR3, plus RSTSAR for security attribution) without duplicating or changing anything in ra8_system_regs.h.

Map (Reset block subset)

Offset	Reg	Width	Purpose
0x0C0	RSTSR1	32	Reset Status Register 1 (W,SW,WDT,LM,...)
0x3C4	RSTSAR	32	Reset Security Attribution Register
0xA40	RSTSR0	8	Reset Status Register 0 (POR, LVD, DPSRSTF)
0xA44	RSTSR2	8	Reset Status Register 2 (CWSF)
0xA48	RSTSR3	8	Reset Status Register 3 (CVMRF, OCPRF, TEMPRF)

The "Software Reset Register" (SWRR) called out in the task brief is not a SYSC register on the RA8D2 – the HUM Ch 6.1 p 244 entry for "Software reset" reads:

Register setting (use the software reset bit AIRCR.SYSRESETREQ)

That is the ARMv8-M System Control Block AIRCR register at 0xE000_ED0C. ra8_reset_software_reset() therefore writes AIRCR with the mandatory 0x05FA write-key in the upper half-word and the SYSRESETREQ bit set, exactly as CMSIS NVIC_SystemReset does. The constants for the AIRCR access live below alongside the other reset-related register addresses so the driver implementation has a single include for everything it touches.

Bit layout reference

Verified against:

HUM Ch 6.2.2 "RSTSR0", p 257-258
HUM Ch 6.2.3 "RSTSR1", p 258-260
HUM Ch 6.2.4 "RSTSR2", p 261
HUM Ch 6.2.5 "RSTSR3", p 261-262
HUM Ch 6.2.1 "RSTSAR", p 256
FSP CMSIS R7KA8D2KF_core0.h R_SYSTEM_Type (lines 15205, 15731, 16645, 16664, 16677) for bit-position cross-check.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_reset_regs.h.

Enumeration Type Documentation

◆ ra8_reset_addr_t

enum ra8_reset_addr_t : uintptr_t

Memory-mapped base addresses used by the reset driver.

Enumerator
k_ra8_reset_sysc_base_addr	R_SYSTEM (SYSC) base.
k_ra8_reset_scb_aircr_addr	Cortex-M85 SCB AIRCR (software reset).

Definition at line 82 of file ra8_reset_regs.h.

◆ ra8_reset_aircr_t

enum ra8_reset_aircr_t : uint32_t

AIRCR fields touched when triggering a software reset.

Per ARMv8-M Architecture Reference Manual / DDI0489 Sec B3.2.6, the Application Interrupt and Reset Control Register at 0xE000ED0C requires the upper 16 bits to carry the magic key 0x05FA on every write or the access is ignored. SYSRESETREQ asks the system controller to schedule a system reset.

HUM Ch 6.1 p 244 explicitly names this as the software-reset path: "Software reset / Source / Register setting (use the software reset bit AIRCR.SYSRESETREQ)".

Enumerator
k_ra8_reset_aircr_vectkey_pos	VECTKEY field position.
k_ra8_reset_aircr_vectkey_value	Mandatory write key.
k_ra8_reset_aircr_sysresetreq_pos	SYSRESETREQ bit pos.
k_ra8_reset_aircr_sysresetreq_msk	SYSRESETREQ mask.

Definition at line 330 of file ra8_reset_regs.h.

◆ ra8_reset_offset_t

enum ra8_reset_offset_t : uint16_t

Offset (within SYSC) of every register the reset driver touches.

Mirrored from ra8_system_regs.h::ra8_system_offset_t for the three RSTSR registers, plus the RSTSR3 and RSTSAR offsets the shared header does not yet expose.

Enumerator
k_ra8_reset_off_rstsr1	RSTSR1 (32-bit). HUM Ch 6.2.3 p 258.
k_ra8_reset_off_prcr	PRCR (16-bit) write-protect. HUM Ch 11.2.18 p 456.
k_ra8_reset_off_rstsar	RSTSAR (32-bit). HUM Ch 6.2.1 p 256.
k_ra8_reset_off_rstsr0	RSTSR0 (8-bit). HUM Ch 6.2.2 p 257.
k_ra8_reset_off_rstsr2	RSTSR2 (8-bit). HUM Ch 6.2.4 p 261.
k_ra8_reset_off_rstsr3	RSTSR3 (8-bit). HUM Ch 6.2.5 p 261.
k_ra8_reset_off_syrstmsk0	SYRSTMSK0 (8-bit). HUM Ch 6.2.6 p 262.
k_ra8_reset_off_syrstmsk1	SYRSTMSK1 (8-bit). HUM Ch 6.2.7 p 263.
k_ra8_reset_off_syrstmsk2	SYRSTMSK2 (8-bit). HUM Ch 6.2.8 p 263.
k_ra8_reset_off_temprcr	TEMPRCR (8-bit). HUM Ch 6.2.9 p 264.
k_ra8_reset_off_temprlr	TEMPRLR (8-bit). HUM Ch 6.2.10 p 265.

Definition at line 101 of file ra8_reset_regs.h.

◆ ra8_reset_prcr_bits_t

enum ra8_reset_prcr_bits_t : uint16_t

PRCR (Protect Register) password + PRC5 enable bit.

SYRSTMSK0/1/2, TEMPRCR and TEMPRLR are write-protected behind PRCR.PRC5. A 16-bit write must carry the 0xA5 password in the upper byte; PRC5 (bit 5) enables writes to the reset-control group.

Enumerator
k_ra8_reset_prcr_key	Mandatory 0xA5 password, upper byte.
k_ra8_reset_prcr_prc5_msk	PRC5: reset-control register group.
k_ra8_reset_prcr_pr_bits_msk	Writable PR0..PR7 enable bits (low byte).

Definition at line 124 of file ra8_reset_regs.h.

◆ ra8_reset_syrstmsk0_bits_t

enum ra8_reset_syrstmsk0_bits_t : uint8_t

SYRSTMSK0 mask bits (1 = reset disabled).

HUM Ch 6.2.6 p 262.

Enumerator
k_ra8_reset_syrstmsk0_iwdt_msk	IWDTMASK: independent WDT reset.
k_ra8_reset_syrstmsk0_wdt0_msk	WDT0MASK: CPU0 WDT reset.
k_ra8_reset_syrstmsk0_sw_msk	SWMASK: software reset.
k_ra8_reset_syrstmsk0_clu0_msk	CLU0MASK: CPU0 lockup reset.
k_ra8_reset_syrstmsk0_lm0_msk	LM0MASK: local-memory-0 error.
k_ra8_reset_syrstmsk0_cm_msk	CMMASK: common-memory error.
k_ra8_reset_syrstmsk0_bus_msk	BUSMASK: bus error reset.

Definition at line 134 of file ra8_reset_regs.h.

◆ ra8_reset_syrstmsk1_bits_t

enum ra8_reset_syrstmsk1_bits_t : uint8_t

SYRSTMSK1 mask bits (1 = reset disabled).

HUM Ch 6.2.7 p 263.

Enumerator
k_ra8_reset_syrstmsk1_wdt1_msk	WDT1MASK: CPU1 WDT reset.
k_ra8_reset_syrstmsk1_clu1_msk	CLU1MASK: CPU1 lockup reset.
k_ra8_reset_syrstmsk1_lm1_msk	LM1MASK: local-memory-1 error.

Definition at line 148 of file ra8_reset_regs.h.

◆ ra8_reset_syrstmsk2_bits_t

enum ra8_reset_syrstmsk2_bits_t : uint8_t

SYRSTMSK2 mask bits (1 = reset disabled).

HUM Ch 6.2.8 p 263.

Enumerator
k_ra8_reset_syrstmsk2_pvd1_msk	PVD1MASK: voltage-monitor-1 reset.
k_ra8_reset_syrstmsk2_pvd2_msk	PVD2MASK: voltage-monitor-2 reset.

Definition at line 158 of file ra8_reset_regs.h.

◆ ra8_reset_temprcr_bits_t

enum ra8_reset_temprcr_bits_t : uint8_t

TEMPRCR (Temperature Monitor Reset Control) bits.

HUM Ch 6.2.9 p 264.

Enumerator
k_ra8_reset_temprcr_tempren_msk	TEMPREN: temperature reset enable.
k_ra8_reset_temprcr_tsnen_msk	TSNEN: temperature sensor enable.
k_ra8_reset_temprcr_cmpen_msk	CMPEN: comparator enable.
k_ra8_reset_temprcr_tsnkeep_msk	TSNKEEP: 1 = close sensor latch.

Definition at line 167 of file ra8_reset_regs.h.

◆ ra8_reset_temprlr_bits_t

enum ra8_reset_temprlr_bits_t : uint8_t

TEMPRLR (Temperature Monitor Reset Lock) bits.

HUM Ch 6.2.10 p 265.

Enumerator
k_ra8_reset_temprlr_lock_msk	LOCK: 1 = TEMPRCR locked (reset value).

Definition at line 178 of file ra8_reset_regs.h.

◆ ra8_rstsar_bits_t

enum ra8_rstsar_bits_t : uint32_t

RSTSAR bit positions / masks (per HUM Ch 6.2.1 p 256).

Each NONSECn bit selects whether the matching reset cause's detect flag and mask register is reachable from non-secure side. On the RA8D2 the field is 5 bits wide (FSP CMSIS lines 15735-15740); higher bits read as 0.

Enumerator
k_ra8_reset_rstsar_nonsec0_pos	NONSEC0 position.
k_ra8_reset_rstsar_nonsec1_pos	NONSEC1 position.
k_ra8_reset_rstsar_nonsec2_pos	NONSEC2 position.
k_ra8_reset_rstsar_nonsec3_pos	NONSEC3 position.
k_ra8_reset_rstsar_nonsec4_pos	NONSEC4 position.
k_ra8_reset_rstsar_field_msk	Defined bit window.

Definition at line 300 of file ra8_reset_regs.h.

◆ ra8_rstsr0_bits_t

enum ra8_rstsr0_bits_t : uint8_t

RSTSR0 bit positions / masks.

Per HUM Ch 6.2.2 p 257-258. Each flag is set by hardware when the matching reset cause fires and is cleared by software using the write-1-then-0 protocol described in HUM Ch 6.2.2 p 258 Note: "Only 0 can be written. To write 0, the bit must be read as 1 first."

Enumerator
k_ra8_reset_rstsr0_porf_pos	PORF: Power-On Reset.
k_ra8_reset_rstsr0_lvd0rf_pos	LVD0RF: Voltage Monitor 0.
k_ra8_reset_rstsr0_lvd1rf_pos	LVD1RF: Voltage Monitor 1.
k_ra8_reset_rstsr0_lvd2rf_pos	LVD2RF: Voltage Monitor 2.
k_ra8_reset_rstsr0_lvd4rf_pos	LVD4RF: Voltage Monitor 4.
k_ra8_reset_rstsr0_lvd5rf_pos	LVD5RF: Voltage Monitor 5.
k_ra8_reset_rstsr0_dpsrstf_pos	DPSRSTF: Deep SW Standby.
k_ra8_reset_rstsr0_porf_msk	PORF mask.
k_ra8_reset_rstsr0_lvd0rf_msk	LVD0RF mask.
k_ra8_reset_rstsr0_lvd1rf_msk	LVD1RF mask.
k_ra8_reset_rstsr0_lvd2rf_msk	LVD2RF mask.
k_ra8_reset_rstsr0_lvd4rf_msk	LVD4RF mask.
k_ra8_reset_rstsr0_lvd5rf_msk	LVD5RF mask.
k_ra8_reset_rstsr0_dpsrstf_msk	DPSRSTF mask.

Definition at line 198 of file ra8_reset_regs.h.

◆ ra8_rstsr1_bits_t

enum ra8_rstsr1_bits_t : uint32_t

RSTSR1 bit positions and masks.

Per HUM Ch 6.2.3 p 258-260 and FSP CMSIS R7KA8D2KF_core0.h lines 15205-15226. Reserved bits read as 0 and write as 0.

Enumerator
k_ra8_reset_rstsr1_iwdtrf_pos	IWDTRF.
k_ra8_reset_rstsr1_wdtrf_pos	WDTRF (CPU0).
k_ra8_reset_rstsr1_swrf_pos	SWRF.
k_ra8_reset_rstsr1_clurf_pos	CLURF (CPU0).
k_ra8_reset_rstsr1_lm0rf_pos	LM0RF.
k_ra8_reset_rstsr1_bussrf_pos	BUSSRF.
k_ra8_reset_rstsr1_cmrf_pos	CMRF.
k_ra8_reset_rstsr1_wdt1rf_pos	WDT1RF (CPU1).
k_ra8_reset_rstsr1_clu1rf_pos	CLU1RF (CPU1).
k_ra8_reset_rstsr1_lm1rf_pos	LM1RF.
k_ra8_reset_rstsr1_nwrf_pos	NWRF (Network).
k_ra8_reset_rstsr1_iwdtrf_msk	IWDTRF mask.
k_ra8_reset_rstsr1_wdtrf_msk	WDTRF mask.
k_ra8_reset_rstsr1_swrf_msk	SWRF mask.
k_ra8_reset_rstsr1_clurf_msk	CLURF mask.
k_ra8_reset_rstsr1_lm0rf_msk	LM0RF mask.
k_ra8_reset_rstsr1_bussrf_msk	BUSSRF mask.
k_ra8_reset_rstsr1_cmrf_msk	CMRF mask.
k_ra8_reset_rstsr1_wdt1rf_msk	WDT1RF mask.
k_ra8_reset_rstsr1_clu1rf_msk	CLU1RF mask.
k_ra8_reset_rstsr1_lm1rf_msk	LM1RF mask.
k_ra8_reset_rstsr1_nwrf_msk	NWRF mask.

Definition at line 228 of file ra8_reset_regs.h.

◆ ra8_rstsr2_bits_t

enum ra8_rstsr2_bits_t : uint8_t

RSTSR2 bit positions / masks (per HUM Ch 6.2.4 p 261).

Enumerator
k_ra8_reset_rstsr2_cwsf_pos	CWSF: 0 = cold start, 1 = warm start.
k_ra8_reset_rstsr2_cwsf_msk	CWSF mask.

Definition at line 262 of file ra8_reset_regs.h.

◆ ra8_rstsr3_bits_t

enum ra8_rstsr3_bits_t : uint8_t

RSTSR3 bit positions / masks (per HUM Ch 6.2.5 p 261-262).

Enumerator
k_ra8_reset_rstsr3_cvmrf_pos	CVMRF: Core voltage monitor.
k_ra8_reset_rstsr3_ocprf_pos	OCPRF: Overcurrent protection.
k_ra8_reset_rstsr3_temprf_pos	TEMPRF: Temperature monitor.
k_ra8_reset_rstsr3_cvmrf_msk	CVMRF mask.
k_ra8_reset_rstsr3_ocprf_msk	OCPRF mask.
k_ra8_reset_rstsr3_temprf_msk	TEMPRF mask.