ra8_reset_regs.h

Go to the documentation of this file.

 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
/* =============================================================================
 * Base addresses
 * =============================================================================
 *
 * The reset block lives inside SYSC. We re-state the base here so the
 * driver does not need to pull in ra8_system_regs.h just to learn
 * where SYSC sits (avoids a transitive include of every CGC / PRCR
 * helper). The literal value matches ``k_ra8_system_base_addr`` in
 * ``ra8_system_regs.h``; this is checked at compile time below.
 */

typedef enum : uintptr_t {
  k_ra8_reset_sysc_base_addr = 0x4001E000UL, 
  k_ra8_reset_scb_aircr_addr = 0xE000ED0CUL, 
} ra8_reset_addr_t;
 
/* =============================================================================
 * Per-register byte offsets within the SYSC block
 * =============================================================================
 */

typedef enum : uint16_t {
  k_ra8_reset_off_rstsr1    = 0x0C0U, 
  k_ra8_reset_off_prcr      = 0x3FAU, 
  k_ra8_reset_off_rstsar    = 0x3C4U, 
  k_ra8_reset_off_rstsr0    = 0xA40U, 
  k_ra8_reset_off_rstsr2    = 0xA44U, 
  k_ra8_reset_off_rstsr3    = 0xA48U, 
  k_ra8_reset_off_syrstmsk0 = 0xAD0U, 
  k_ra8_reset_off_syrstmsk1 = 0xAD4U, 
  k_ra8_reset_off_syrstmsk2 = 0xAD8U, 
  k_ra8_reset_off_temprcr   = 0xADCU, 
  k_ra8_reset_off_temprlr   = 0xAE0U, 
} ra8_reset_offset_t;

typedef enum : uint16_t {
  k_ra8_reset_prcr_key         = 0xA500U, 
  k_ra8_reset_prcr_prc5_msk    = 0x0020U, 
  k_ra8_reset_prcr_pr_bits_msk = 0x00FFU, 
} ra8_reset_prcr_bits_t;

typedef enum : uint8_t {
  k_ra8_reset_syrstmsk0_iwdt_msk = 0x01U, 
  k_ra8_reset_syrstmsk0_wdt0_msk = 0x02U, 
  k_ra8_reset_syrstmsk0_sw_msk   = 0x04U, 
  k_ra8_reset_syrstmsk0_clu0_msk = 0x10U, 
  k_ra8_reset_syrstmsk0_lm0_msk  = 0x20U, 
  k_ra8_reset_syrstmsk0_cm_msk   = 0x40U, 
  k_ra8_reset_syrstmsk0_bus_msk  = 0x80U, 
} ra8_reset_syrstmsk0_bits_t;

typedef enum : uint8_t {
  k_ra8_reset_syrstmsk1_wdt1_msk = 0x02U, 
  k_ra8_reset_syrstmsk1_clu1_msk = 0x10U, 
  k_ra8_reset_syrstmsk1_lm1_msk  = 0x20U, 
} ra8_reset_syrstmsk1_bits_t;

typedef enum : uint8_t {
  k_ra8_reset_syrstmsk2_pvd1_msk = 0x01U, 
  k_ra8_reset_syrstmsk2_pvd2_msk = 0x02U, 
} ra8_reset_syrstmsk2_bits_t;

typedef enum : uint8_t {
  k_ra8_reset_temprcr_tempren_msk = 0x01U, 
  k_ra8_reset_temprcr_tsnen_msk   = 0x02U, 
  k_ra8_reset_temprcr_cmpen_msk   = 0x04U, 
  k_ra8_reset_temprcr_tsnkeep_msk = 0x08U, 
} ra8_reset_temprcr_bits_t;

typedef enum : uint8_t {
  k_ra8_reset_temprlr_lock_msk = 0x01U, 
} ra8_reset_temprlr_bits_t;
 
/* =============================================================================
 * RSTSR0 -- 8-bit (Power-on / voltage-monitor / Deep-software-standby)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_reset_rstsr0_porf_pos    = 0U,    
  k_ra8_reset_rstsr0_lvd0rf_pos  = 1U,    
  k_ra8_reset_rstsr0_lvd1rf_pos  = 2U,    
  k_ra8_reset_rstsr0_lvd2rf_pos  = 3U,    
  k_ra8_reset_rstsr0_lvd4rf_pos  = 5U,    
  k_ra8_reset_rstsr0_lvd5rf_pos  = 6U,    
  k_ra8_reset_rstsr0_dpsrstf_pos = 7U,    
  k_ra8_reset_rstsr0_porf_msk    = 0x01U, 
  k_ra8_reset_rstsr0_lvd0rf_msk  = 0x02U, 
  k_ra8_reset_rstsr0_lvd1rf_msk  = 0x04U, 
  k_ra8_reset_rstsr0_lvd2rf_msk  = 0x08U, 
  k_ra8_reset_rstsr0_lvd4rf_msk  = 0x20U, 
  k_ra8_reset_rstsr0_lvd5rf_msk  = 0x40U, 
  k_ra8_reset_rstsr0_dpsrstf_msk = 0x80U, 
} ra8_rstsr0_bits_t;
 
/* =============================================================================
 * RSTSR1 -- 32-bit (IWDT / WDT / SW / Lockup / LM / BUS / CM / WDT1 / NW)
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_reset_rstsr1_iwdtrf_pos = 0U,           
  k_ra8_reset_rstsr1_wdtrf_pos  = 1U,           
  k_ra8_reset_rstsr1_swrf_pos   = 2U,           
  k_ra8_reset_rstsr1_clurf_pos  = 4U,           
  k_ra8_reset_rstsr1_lm0rf_pos  = 5U,           
  k_ra8_reset_rstsr1_bussrf_pos = 10U,          
  k_ra8_reset_rstsr1_cmrf_pos   = 14U,          
  k_ra8_reset_rstsr1_wdt1rf_pos = 17U,          
  k_ra8_reset_rstsr1_clu1rf_pos = 20U,          
  k_ra8_reset_rstsr1_lm1rf_pos  = 21U,          
  k_ra8_reset_rstsr1_nwrf_pos   = 22U,          
  k_ra8_reset_rstsr1_iwdtrf_msk = 0x00000001UL, 
  k_ra8_reset_rstsr1_wdtrf_msk  = 0x00000002UL, 
  k_ra8_reset_rstsr1_swrf_msk   = 0x00000004UL, 
  k_ra8_reset_rstsr1_clurf_msk  = 0x00000010UL, 
  k_ra8_reset_rstsr1_lm0rf_msk  = 0x00000020UL, 
  k_ra8_reset_rstsr1_bussrf_msk = 0x00000400UL, 
  k_ra8_reset_rstsr1_cmrf_msk   = 0x00004000UL, 
  k_ra8_reset_rstsr1_wdt1rf_msk = 0x00020000UL, 
  k_ra8_reset_rstsr1_clu1rf_msk = 0x00100000UL, 
  k_ra8_reset_rstsr1_lm1rf_msk  = 0x00200000UL, 
  k_ra8_reset_rstsr1_nwrf_msk   = 0x00400000UL, 
} ra8_rstsr1_bits_t;
 
/* =============================================================================
 * RSTSR2 -- 8-bit (Cold/Warm Start)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_reset_rstsr2_cwsf_pos = 0U,    
  k_ra8_reset_rstsr2_cwsf_msk = 0x01U, 
} ra8_rstsr2_bits_t;
 
/* =============================================================================
 * RSTSR3 -- 8-bit (Core voltage / Overcurrent / Temperature)
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_reset_rstsr3_cvmrf_pos  = 0U,    
  k_ra8_reset_rstsr3_ocprf_pos  = 4U,    
  k_ra8_reset_rstsr3_temprf_pos = 7U,    
  k_ra8_reset_rstsr3_cvmrf_msk  = 0x01U, 
  k_ra8_reset_rstsr3_ocprf_msk  = 0x10U, 
  k_ra8_reset_rstsr3_temprf_msk = 0x80U, 
} ra8_rstsr3_bits_t;
 
/* =============================================================================
 * RSTSAR -- 32-bit Reset Security Attribution
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_reset_rstsar_nonsec0_pos = 0U, 
  k_ra8_reset_rstsar_nonsec1_pos = 1U, 
  k_ra8_reset_rstsar_nonsec2_pos = 2U, 
  k_ra8_reset_rstsar_nonsec3_pos = 3U, 
  k_ra8_reset_rstsar_nonsec4_pos = 4U, 
  k_ra8_reset_rstsar_field_msk   = 0x0000001FUL,
} ra8_rstsar_bits_t;
 
/* =============================================================================
 * SCB AIRCR (Cortex-M85) -- used by ra8_reset_software_reset()
 * =============================================================================
 */

typedef enum : uint32_t {
  k_ra8_reset_aircr_vectkey_pos     = 16U,          
  k_ra8_reset_aircr_vectkey_value   = 0x05FAUL,     
  k_ra8_reset_aircr_sysresetreq_pos = 2U,           
  k_ra8_reset_aircr_sysresetreq_msk = 0x00000004UL, 
} ra8_reset_aircr_t;
 
/* =============================================================================
 * Inline pointer accessors
 * =============================================================================
 *
 * Accessors return ``volatile`` pointers to the underlying register so
 * the host-side ``ra8_fake_mmap`` shim can intercept reads / writes
 * without any conditional compilation in the driver.
 */

static inline volatile uint8_t* ra8_reset_rstsr0(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_rstsr0);
}

static inline volatile uint32_t* ra8_reset_rstsr1(void)
{
  return (volatile uint32_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_rstsr1);
}

static inline volatile uint8_t* ra8_reset_rstsr2(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_rstsr2);
}

static inline volatile uint8_t* ra8_reset_rstsr3(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_rstsr3);
}

static inline volatile uint32_t* ra8_reset_rstsar(void)
{
  return (volatile uint32_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_rstsar);
}

static inline volatile uint32_t* ra8_reset_aircr(void)
{
  return (volatile uint32_t*)k_ra8_reset_scb_aircr_addr;
}

static inline volatile uint16_t* ra8_reset_prcr(void)
{
  return (volatile uint16_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_prcr);
}

static inline volatile uint8_t* ra8_reset_syrstmsk0(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_syrstmsk0);
}

static inline volatile uint8_t* ra8_reset_syrstmsk1(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_syrstmsk1);
}

static inline volatile uint8_t* ra8_reset_syrstmsk2(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_syrstmsk2);
}

static inline volatile uint8_t* ra8_reset_temprcr(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_temprcr);
}

static inline volatile uint8_t* ra8_reset_temprlr(void)
{
  return (volatile uint8_t*)(k_ra8_reset_sysc_base_addr + (uintptr_t)k_ra8_reset_off_temprlr);
}
 
#ifdef __cplusplus
}
#endif