ra8_npu_regs.h File Reference

Arm Ethos-U55 NPU register window on the Renesas RA8P1 (RA8P1-only). More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_device.h"

Include dependency graph for ra8_npu_regs.h:

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Go to the source code of this file.

Enumerations
enum	ra8_npu_addr_t : uintptr_t { k_ra8_npu_base_addr = 0x40140000U }
	Ethos-U55 register-window base and extent on the RA8P1. More...
enum	ra8_npu_layout_t : uint32_t {   k_ra8_npu_window_bytes = 0x1000U ,   k_ra8_npu_off_id = 0x0000U ,   k_ra8_npu_off_status = 0x0004U ,   k_ra8_npu_off_cmd = 0x0008U ,   k_ra8_npu_off_reset = 0x000CU ,   k_ra8_npu_off_qbase_lo = 0x0010U ,   k_ra8_npu_off_qbase_hi = 0x0014U ,   k_ra8_npu_off_qread = 0x0018U ,   k_ra8_npu_off_qconfig = 0x001CU ,   k_ra8_npu_off_qsize = 0x0020U ,   k_ra8_npu_off_prot = 0x0024U ,   k_ra8_npu_off_config = 0x0028U ,   k_ra8_npu_off_regioncfg = 0x003CU ,   k_ra8_npu_off_basep0_lo = 0x0080U }
	Byte offsets of the Ethos-U55 APB registers within the window. More...
enum	ra8_npu_region_idx_t : uint8_t {   k_ra8_npu_region_0 = 0U ,   k_ra8_npu_region_1 = 1U ,   k_ra8_npu_region_2 = 2U ,   k_ra8_npu_region_3 = 3U ,   k_ra8_npu_region_4 = 4U ,   k_ra8_npu_region_5 = 5U ,   k_ra8_npu_region_6 = 6U ,   k_ra8_npu_region_7 = 7U ,   k_ra8_npu_region_count = 8U }
	Base-pointer region indices (Ethos-U55 has eight AXI region bases). More...
enum	ra8_npu_geom_t : uint32_t {   k_ra8_npu_reg_hi_offset = 0x0004U ,   k_ra8_npu_basep_stride_bytes = 0x0008U }
	Geometry of the 64-bit register pairs (QBASE, BASEPn). More...
enum	ra8_npu_cmd_bit_t : uint8_t {   k_ra8_npu_cmd_run_bit = 0U ,   k_ra8_npu_cmd_clear_irq_bit = 1U ,   k_ra8_npu_cmd_clock_q_bit = 2U ,   k_ra8_npu_cmd_power_q_bit = 3U }
	Bit positions in the NPU_CMD register. More...
enum	ra8_npu_status_bit_t : uint8_t {   k_ra8_npu_status_state_bit = 0U ,   k_ra8_npu_status_irq_raised_bit = 1U ,   k_ra8_npu_status_bus_error_bit = 2U ,   k_ra8_npu_status_reset_bit = 3U ,   k_ra8_npu_status_cmd_parse_bit = 4U ,   k_ra8_npu_status_cmd_end_bit = 5U ,   k_ra8_npu_status_pmu_irq_bit = 6U ,   k_ra8_npu_status_wd_fault_bit = 7U ,   k_ra8_npu_status_ecc_fault_bit = 8U }
	Bit positions in the NPU_STATUS register. More...
enum	ra8_npu_reset_bit_t : uint8_t {   k_ra8_npu_reset_pending_cpl_bit = 0U ,   k_ra8_npu_reset_pending_csl_bit = 1U }
	Bit positions in the NPU_RESET register. More...
enum	ra8_npu_event_t : uint16_t { k_ra8_npu_event_irq = 0x067U }
	ICU/ELC event number for the NPU interrupt. More...

Functions
static volatile uint32_t *	ra8_npu_reg (uint32_t byte_off)
	Compute a volatile pointer to an NPU register by byte offset.

Detailed Description

Arm Ethos-U55 NPU register window on the Renesas RA8P1 (RA8P1-only).

The RA8P1 (R7KA8P1KFLCAC) integrates an Arm Ethos-U55 micro-NPU that the RA8D2 does not have. This header exposes the register window base, the command / queue / base-pointer interface offsets, and the CMD / STATUS / RESET field bits so ra8_npu.c can drive an inference job out of shared system SRAM.

Sourcing (no invented registers)

The window base, size, interrupt event, module-stop bit, and clock domain are CONFIRMED constants cross-validated across the RA8P1 FSP CMSIS device header R7KA8P1KF_core0.h and the Zephyr r7ka8p1xf.dtsi, which agree exactly. The register OFFSETS and field-bit layout below are the Arm Ethos-U55 architectural APB interface, transcribed from the "Arm Ethos-U55 NPU Technical Reference Manual" register map and cross-checked byte-for-byte against Arm's open ethos-u-core-driver ethosu_interface.h (both REFERENCE-ONLY: the offsets are hardware facts, the prose and enums here are hand-authored under this project's style). This is deliberately NOT the RSIP-style invented- register fiction the project has been burned by before – every offset traces to the published Ethos-U55 interface. On-silicon behaviour is UNPROVEN (there is no RA8P1 board yet); the driver foundation is host-tested for the register write sequence only, and a real inference is a follow-up.

Confirmed integration facts:

• Register window base 0x40140000, size 0x1000 (4 KiB).
• Peripheral event (ELC/ICU) NPU_IRQ = 0x067.
• Module-stop bit: MSTPCRA bit 16 (see ra8_mstp_regs.h).
• Clock: dedicated NPUCLK domain, SCKDIVCR2[11:8] (already modelled in ra8_cgc_regs.h), up to 500 MHz.
• Compute: 256 8x8 MAC units (~256 GOPS), 8/16-bit quantized CNN + RNN.
• The NPU has no dedicated CPU-visible SRAM: it works out of the shared on-chip system SRAM (k_ra8_mem_sram_base) over AXI, plus a small internal SHRAM (8-48 KiB, not memory-mapped to the CPU).

Note

Compiled into RA8P1 targets only. It is guarded so an accidental include on an RA8D2 build fails loudly rather than pretending the NPU exists.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file ra8_npu_regs.h.

Enumeration Type Documentation

ra8_npu_addr_t

enum ra8_npu_addr_t : uintptr_t

Ethos-U55 register-window base and extent on the RA8P1.

Address constants for the NPU peripheral. uintptr_t so the base is a correct pointer on both the 32-bit target and the 64-bit test host.

Invariant

k_ra8_npu_base_addr is 4 KiB aligned.

See also

ra8_npu_reg

Since

0.1.0

Enumerator
k_ra8_npu_base_addr	R_NPU register window base (Ethos-U55).

Definition at line 75 of file ra8_npu_regs.h.

ra8_npu_cmd_bit_t

enum ra8_npu_cmd_bit_t : uint8_t

Bit positions in the NPU_CMD register.

Writing 1 to k_ra8_npu_cmd_run_bit transitions the NPU into the running state and it begins parsing the command queue. Writing 1 to k_ra8_npu_cmd_clear_irq_bit acknowledges (clears) a raised IRQ. The clock/power Q-enable bits gate the internal power/clock quiescence handshakes and are held enabled while a job runs.

Invariant

Each value is a valid 0-based bit index in a 32-bit register.

See also

ra8_npu_status_bit_t

Since

0.1.0

Enumerator
k_ra8_npu_cmd_run_bit	transition_to_running_state (start job).
k_ra8_npu_cmd_clear_irq_bit	clear_irq (write 1 to acknowledge IRQ).
k_ra8_npu_cmd_clock_q_bit	clock_q_enable.
k_ra8_npu_cmd_power_q_bit	power_q_enable.

Definition at line 172 of file ra8_npu_regs.h.

ra8_npu_event_t

enum ra8_npu_event_t : uint16_t

ICU/ELC event number for the NPU interrupt.

Route this event to an NVIC line via the ICU IELSR registers the same way any other peripheral event is routed (see ra8_icu_regs.h / ra8_isr_register). This number occupies a slot that is a reserved gap in the RA8D2 event space, so it does not collide with any shared event.

Invariant

Value is a valid elc_event_t index on the RA8P1.

Since

0.1.0

Enumerator
k_ra8_npu_event_irq	NPU_IRQ event (RA8P1 elc_event_t).

Definition at line 236 of file ra8_npu_regs.h.

ra8_npu_geom_t

enum ra8_npu_geom_t : uint32_t

Geometry of the 64-bit register pairs (QBASE, BASEPn).

Ethos-U55 addresses are 64-bit and split across two consecutive 32-bit words: a low word then a high word k_ra8_npu_reg_hi_offset bytes above it. Consecutive BASEPn pairs are k_ra8_npu_basep_stride_bytes apart.

Invariant

k_ra8_npu_basep_stride_bytes == 2 * k_ra8_npu_reg_hi_offset.

See also

ra8_npu_region_idx_t

Since

0.1.0

Enumerator
k_ra8_npu_reg_hi_offset	Low->high word gap in a 64-bit reg.
k_ra8_npu_basep_stride_bytes	Bytes between BASEPn pairs (lo+hi).

Definition at line 153 of file ra8_npu_regs.h.

ra8_npu_layout_t

enum ra8_npu_layout_t : uint32_t

Byte offsets of the Ethos-U55 APB registers within the window.

Word-aligned byte offsets into the 4 KiB window, transcribed from the Ethos-U55 TRM register map (see the file header for sourcing). The command queue is the CPU->NPU submission channel: QBASE (lo/hi 64-bit) points at the Vela command stream in SRAM and QSIZE gives its byte length. The eight base-pointer regions (see k_ra8_npu_off_basep0_lo and ra8_npu_region_idx_t) supply the AXI base address of each tensor arena the command stream references.

Invariant

Every offset is < k_ra8_npu_window_bytes and 4-byte aligned.

See also

ra8_npu_reg

Since

0.1.0

Enumerator
k_ra8_npu_window_bytes	4 KiB register window.
k_ra8_npu_off_id	NPU_ID (Arm Ethos-U arch id/revision).
k_ra8_npu_off_status	NPU_STATUS (state + fault flags, RO).
k_ra8_npu_off_cmd	NPU_CMD (run / clear-irq / q-enables).
k_ra8_npu_off_reset	NPU_RESET (software reset request).
k_ra8_npu_off_qbase_lo	QBASE bits [31:0] (cmd-stream address).
k_ra8_npu_off_qbase_hi	QBASE bits [63:32].
k_ra8_npu_off_qread	QREAD (cmd-stream read offset, RO).
k_ra8_npu_off_qconfig	QCONFIG (cmd-stream AXI region config).
k_ra8_npu_off_qsize	QSIZE (cmd-stream length in bytes).
k_ra8_npu_off_prot	NPU_PROT (privilege/security, RO).
k_ra8_npu_off_config	NPU_CONFIG (build-time macs/rev, RO).
k_ra8_npu_off_regioncfg	REGIONCFG (per-region AXI attributes).
k_ra8_npu_off_basep0_lo	BASEP0 bits [31:0] (region 0 base).

Definition at line 95 of file ra8_npu_regs.h.

ra8_npu_region_idx_t

enum ra8_npu_region_idx_t : uint8_t

Base-pointer region indices (Ethos-U55 has eight AXI region bases).

The Vela command stream addresses tensors by region index; the CPU programs the actual AXI base of each region into the BASEPn register pair before running a job. BASEPn_lo sits at k_ra8_npu_off_basep0_lo + n * k_ra8_npu_basep_stride_bytes, and its high word k_ra8_npu_reg_hi_offset bytes above that. Region 0 is the read-only weight/bias arena by Vela convention; other regions hold the scratch, input, and output tensors.

Invariant

k_ra8_npu_region_count equals the number of BASEPn register pairs.

See also

ra8_npu_geom_t

Since

0.1.0

Enumerator
k_ra8_npu_region_0	AXI region 0 (weights/biases by convention).
k_ra8_npu_region_1	AXI region 1.
k_ra8_npu_region_2	AXI region 2.
k_ra8_npu_region_3	AXI region 3.
k_ra8_npu_region_4	AXI region 4.
k_ra8_npu_region_5	AXI region 5.
k_ra8_npu_region_6	AXI region 6.
k_ra8_npu_region_7	AXI region 7.
k_ra8_npu_region_count	Number of BASEPn region base-pointer pairs.

Definition at line 128 of file ra8_npu_regs.h.

ra8_npu_reset_bit_t

enum ra8_npu_reset_bit_t : uint8_t

Bit positions in the NPU_RESET register.

A write to NPU_RESET requests a soft reset; the target privilege and security levels the NPU adopts on the next run are encoded in these bits. The driver clears both (privileged, secure) and then polls k_ra8_npu_status_reset_bit until the reset completes.

Invariant

Each value is a valid 0-based bit index in a 32-bit register.

See also

ra8_npu_status_bit_t

Since

0.1.0

Enumerator
k_ra8_npu_reset_pending_cpl_bit	Privilege level adopted after reset.
k_ra8_npu_reset_pending_csl_bit	Security level adopted after reset.

Definition at line 218 of file ra8_npu_regs.h.

ra8_npu_status_bit_t

enum ra8_npu_status_bit_t : uint8_t

Bit positions in the NPU_STATUS register.

state reads 1 while the NPU is running and 0 when it has stopped. cmd_end asserts when the command stream is fully consumed. The remaining bits latch fault conditions (bus error, command-stream parse error, weight-decoder fault, internal-SRAM ECC fault) that the driver surfaces as k_ra8_err_hw_error.

Invariant

Each value is a valid 0-based bit index in a 32-bit register.

See also

ra8_npu_cmd_bit_t

Since

0.1.0

Enumerator
k_ra8_npu_status_state_bit	1 = running, 0 = stopped.
k_ra8_npu_status_irq_raised_bit	IRQ asserted by the NPU.
k_ra8_npu_status_bus_error_bit	AXI bus error latched.
k_ra8_npu_status_reset_bit	Reset in progress.
k_ra8_npu_status_cmd_parse_bit	Command-stream parse error.
k_ra8_npu_status_cmd_end_bit	Command stream fully consumed.
k_ra8_npu_status_pmu_irq_bit	Performance-counter IRQ.
k_ra8_npu_status_wd_fault_bit	Weight-decoder fault.
k_ra8_npu_status_ecc_fault_bit	Internal SRAM ECC fault.

Definition at line 193 of file ra8_npu_regs.h.

Function Documentation

ra8_npu_reg()

volatile uint32_t * ra8_npu_reg ( uint32_t byte_off )

inlinestatic

Compute a volatile pointer to an NPU register by byte offset.

Returns k_ra8_npu_base_addr + byte_off as a volatile uint32_t* so ra8_npu.c can read/write a confirmed offset (e.g. k_ra8_npu_off_cmd) with a single word access. This accessor performs NO register access – it only computes an address – so no register citation lives here; the citation sits at each dereference site in the driver. The caller must have released the NPU module-stop bit and enabled NPUCLK before dereferencing the result.

Parameters

[in]

byte_off

Register byte offset from ra8_npu_layout_t (0 .. k_ra8_npu_window_bytes - 4, 4-byte aligned).

Returns

Volatile pointer to the addressed 32-bit NPU register.

Return values

(base+off)

Always the fixed peripheral base plus byte_off (non-NULL).

Precondition

The build targets the RA8P1 (RA8_HAS_NPU defined).

NPU module-stop released and NPUCLK enabled before any dereference.

Postcondition

Returned pointer addresses the requested register; nothing was touched.

No side effects on hardware.

Note

Not thread-safe in the sense of hardware ownership: the caller owns serialisation of NPU access. The pointer computation itself is re-entrant.

See also

ra8_npu_layout_t

Since

0.1.0

Definition at line 269 of file ra8_npu_regs.h.

References k_ra8_npu_base_addr.