ra8_icu_regs.h File Reference

Interrupt Control Unit (ICU) register layout for the Renesas RA8D2. More...

#include <stdint.h>

Include dependency graph for ra8_icu_regs.h:

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Enumerations
enum	ra8_icu_addr_t : uintptr_t { k_ra8_icu_base_addr = 0x40006000UL }
enum	ra8_icu_limits_t : uint16_t {   k_ra8_icu_num_ielsr = 96U ,   k_ra8_icu_num_irqs = 32U ,   k_ra8_icu_irqcra_count = 16U ,   k_ra8_icu_irqcrb_first = 16U ,   k_ra8_icu_irqcrb_offset = 4U }
enum	ra8_icu_off_t : uint32_t {   k_ra8_icu_off_irqcra0 = 0x0000U ,   k_ra8_icu_off_nmicr = 0x0010U ,   k_ra8_icu_off_irqcrb0 = 0x0014U ,   k_ra8_icu_off_intselr = 0x0040U ,   k_ra8_icu_off_nmier = 0x6100U ,   k_ra8_icu_off_nmiclr = 0x6110U ,   k_ra8_icu_off_nmisr = 0x6120U ,   k_ra8_icu_off_wupen0 = 0x61A0U ,   k_ra8_icu_off_wupen1 = 0x61A4U ,   k_ra8_icu_off_dslpwup = 0x6210U ,   k_ra8_icu_off_delsr0 = 0x6280U ,   k_ra8_icu_off_ielsr0 = 0x6300U }
enum	ra8_icu_irqmd_t : uint8_t {   k_ra8_icu_irqmd_falling = 0U ,   k_ra8_icu_irqmd_rising = 1U ,   k_ra8_icu_irqmd_both = 2U ,   k_ra8_icu_irqmd_low = 3U }
	IRQCRi.IRQMD[1:0] detection sense values (HUM 14.2.12 p 535). More...
enum	ra8_icu_fclksel_t : uint8_t {   k_ra8_icu_fclksel_pclkb = 0U ,   k_ra8_icu_fclksel_pclkb_8 = 1U ,   k_ra8_icu_fclksel_pclkb_32 = 2U ,   k_ra8_icu_fclksel_pclkb_64 = 3U }
	IRQCRi.FCLKSEL[1:0] digital filter sampling clock (HUM 14.2.12 p 535). More...
enum	ra8_icu_irqcr_bit_t : uint8_t {   k_ra8_icu_irqcr_bit_fclksel = 4U ,   k_ra8_icu_irqcr_bit_flten = 7U }
	IRQCRi bit positions. More...
enum	ra8_icu_irqcr_mask_t : uint8_t {   k_ra8_icu_irqcr_mask_irqmd = 0x03U ,   k_ra8_icu_irqcr_mask_fclksel = 0x30U ,   k_ra8_icu_irqcr_mask_flten = 0x80U }
	IRQCRi bit masks. More...
enum	ra8_ielsr_bit_t : uint8_t {   k_ra8_ielsr_iels_shift = 0U ,   k_ra8_ielsr_ir_bit = 16U ,   k_ra8_ielsr_dtce_bit = 24U }
	Bit positions in an IELSR register. More...
enum	ra8_ielsr_mask_t : uint32_t {   k_ra8_ielsr_iels_mask = 0x000003FFUL ,   k_ra8_ielsr_ir_mask = 0x00010000UL ,   k_ra8_ielsr_dtce_mask = 0x01000000UL }

Functions
static volatile uint32_t *	ra8_icu_nmier (void)
	Get pointer to the 32-bit NMIER register.
static volatile uint32_t *	ra8_icu_nmisr (void)
	Get pointer to the 32-bit NMISR register.
static volatile uint32_t *	ra8_icu_nmiclr (void)
	Get pointer to the 32-bit NMICLR register.
static volatile uint8_t *	ra8_icu_nmicr (void)
	Get pointer to the 8-bit NMICR register.
static volatile uint32_t *	ra8_icu_wupen0 (void)
	Get pointer to the 32-bit WUPEN0 register.
static volatile uint32_t *	ra8_icu_wupen1 (void)
	Get pointer to the 32-bit WUPEN1 register.
static volatile uint32_t *	ra8_icu_delsr (uint8_t index)
	Get pointer to DELSR[index], the DMAC Event Link Setting Register.
static volatile uint32_t *	ra8_icu_ielsr (uint16_t index)
	Get pointer to IELSR register N.
static volatile uint8_t *	ra8_icu_irqcr (uint8_t irq_num)
	Get pointer to the IRQCRi register for IRQ channel irq_num.

Detailed Description

Interrupt Control Unit (ICU) register layout for the Renesas RA8D2.

The RA Interrupt Control Unit sits between the peripheral event sources and the two Cortex-M NVICs (one per core). Unlike most Cortex-M chips, peripheral interrupt numbers on RA are programmable: you tell the ICU "please route event X to NVIC line Y", then enable line Y in the NVIC as usual. The event-to-line map lives in the IELSR registers below.

Register map (partial)

Offset	Name	Width	Purpose
0x000	IRQCR0-15	8	External IRQ input digital filter
0x100	NMICR	8	NMI pin control
0x300	IELSR0..n	32	Event Link Setting Registers
0x1000	IELSRN0..m	32	(secure copy / non-secure copies)

IELSR usage

// Route SCI0 RXI (event 0x050 from FSP bsp_elc.h) to NVIC line 3.
ra8_icu()->IELSR[3] = 0x050UL;
NVIC_EnableIRQ(3);

Note

The Cortex-M85 core has 480 NVIC interrupts, but only the first N are wired to the ICU – N depends on MCU variant. The Cortex-M33 on RA8D2 sees its own disjoint set.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_icu_regs.h.

Enumeration Type Documentation

ra8_icu_addr_t

enum ra8_icu_addr_t : uintptr_t

Enumerator
k_ra8_icu_base_addr	R_ICU block base.

Definition at line 52 of file ra8_icu_regs.h.

ra8_icu_fclksel_t

enum ra8_icu_fclksel_t : uint8_t

IRQCRi.FCLKSEL[1:0] digital filter sampling clock (HUM 14.2.12 p 535).

Enumerator
k_ra8_icu_fclksel_pclkb	00: sample every PCLKB cycle.
k_ra8_icu_fclksel_pclkb_8	01: sample once per 8 cycles.
k_ra8_icu_fclksel_pclkb_32	10: sample once per 32 cycles.
k_ra8_icu_fclksel_pclkb_64	11: sample once per 64 cycles.

Definition at line 100 of file ra8_icu_regs.h.

ra8_icu_irqcr_bit_t

enum ra8_icu_irqcr_bit_t : uint8_t

IRQCRi bit positions.

Enumerator
k_ra8_icu_irqcr_bit_fclksel	FCLKSEL[1:0] at bits 5..4.
k_ra8_icu_irqcr_bit_flten	FLTEN at bit 7.

Definition at line 111 of file ra8_icu_regs.h.

ra8_icu_irqcr_mask_t

enum ra8_icu_irqcr_mask_t : uint8_t

IRQCRi bit masks.

Enumerator
k_ra8_icu_irqcr_mask_irqmd	IRQMD[1:0] bits 1..0.
k_ra8_icu_irqcr_mask_fclksel	FCLKSEL[1:0] bits 5..4.
k_ra8_icu_irqcr_mask_flten	FLTEN bit 7.

Definition at line 120 of file ra8_icu_regs.h.

ra8_icu_irqmd_t

enum ra8_icu_irqmd_t : uint8_t

IRQCRi.IRQMD[1:0] detection sense values (HUM 14.2.12 p 535).

Enumerator
k_ra8_icu_irqmd_falling	00: falling edge.
k_ra8_icu_irqmd_rising	01: rising edge.
k_ra8_icu_irqmd_both	10: rising OR falling.
k_ra8_icu_irqmd_low	11: low-level sensitive.

Definition at line 89 of file ra8_icu_regs.h.

ra8_icu_limits_t

enum ra8_icu_limits_t : uint16_t

Enumerator
k_ra8_icu_num_ielsr	IELSR slot count on RA8D2 (FSP R_ICU_Type).
k_ra8_icu_num_irqs	IRQ0..IRQ31, RA8D2 has 32 IRQ channels.
k_ra8_icu_irqcra_count	IRQCRa[16] holds channels 0..15.
k_ra8_icu_irqcrb_first	First IRQ channel served by IRQCRb.
k_ra8_icu_irqcrb_offset	Byte gap between IRQCRa[15] and IRQCRb[0].

Definition at line 56 of file ra8_icu_regs.h.

ra8_icu_off_t

enum ra8_icu_off_t : uint32_t

Enumerator
k_ra8_icu_off_irqcra0	IRQCRa[0..15] (8 bits each), ch 0..15.
k_ra8_icu_off_nmicr	NMICR: NMI pin control (8b).
k_ra8_icu_off_irqcrb0	IRQCRb[0..15] (8 bits each), ch 16..31.
k_ra8_icu_off_intselr	INTSELR[32] (32 bits each): IRQ core.
k_ra8_icu_off_nmier	NMIER: NMI enable (32b).
k_ra8_icu_off_nmiclr	NMICLR: NMI status clear (32b).
k_ra8_icu_off_nmisr	NMISR: NMI status (32b).
k_ra8_icu_off_wupen0	WUPEN0: wake-up enable register 0.
k_ra8_icu_off_wupen1	WUPEN1: wake-up enable register 1.
k_ra8_icu_off_dslpwup	DSLPWUPIRQEN[3]: deep-sleep IRQ enable.
k_ra8_icu_off_delsr0	DELSR[8]: DMAC event link select.
k_ra8_icu_off_ielsr0	IELSR[0..95] (32 bits each).

Definition at line 70 of file ra8_icu_regs.h.

ra8_ielsr_bit_t

enum ra8_ielsr_bit_t : uint8_t

Bit positions in an IELSR register.

Cross-checked against FSP R_ICU_Type::IELSR_b[96] in R7KA8D2KF_core0.h: IELS is a 10-bit field at [9:0], IR (interrupt status flag, RW1C) at [16], DTCE at [24]. HUM Ch 14.2.17 "IELSRn : ICU Event Link Setting Register n", p 524.

Enumerator
k_ra8_ielsr_iels_shift	IELS event-select shift, bits [9:0].
k_ra8_ielsr_ir_bit	IR interrupt status flag (W0C).
k_ra8_ielsr_dtce_bit	DTCE: DTC activation enable.

Definition at line 263 of file ra8_icu_regs.h.

ra8_ielsr_mask_t

enum ra8_ielsr_mask_t : uint32_t

Enumerator
k_ra8_ielsr_iels_mask	IELS field mask (10 bits).
k_ra8_ielsr_ir_mask	IR bit mask (RW1C).
k_ra8_ielsr_dtce_mask	DTCE bit mask.

Definition at line 269 of file ra8_icu_regs.h.

Function Documentation

ra8_icu_delsr()

volatile uint32_t * ra8_icu_delsr ( uint8_t index )

inlinestatic

Get pointer to DELSR[index], the DMAC Event Link Setting Register.

DELSR has 8 entries, each a 32-bit register with DELS at [9:0] and IR at [16]. HUM Ch 14 "DELSRn : DMAC Event Link Setting Register n", p 524..582.

Parameters

[in]

index

DELSR slot 0..7.

Returns

Pointer to the slot, or nullptr on out-of-range.

< RA8 icu number delsr.

Definition at line 187 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_delsr0.

ra8_icu_ielsr()

volatile uint32_t * ra8_icu_ielsr ( uint16_t index )

inlinestatic

Get pointer to IELSR register N.

Definition at line 205 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, k_ra8_icu_num_ielsr, and k_ra8_icu_off_ielsr0.

Referenced by dtc_coh_arm_slot(), dtc_demo_arm_slot(), internal_ielsr_clear(), internal_ielsr_write(), ra8_isr_dispatch(), and ra8_isr_set_dtc().

ra8_icu_irqcr()

volatile uint8_t * ra8_icu_irqcr ( uint8_t irq_num )

inlinestatic

Get pointer to the IRQCRi register for IRQ channel irq_num.

RA8D2 has 32 external IRQ channels split across two 16-deep arrays:

• IRQCRa[0..15] at offsets 0x00..0x0F (channels 0..15).
• IRQCRb[0..15] at offsets 0x14..0x23 (channels 16..31), separated from IRQCRa by NMICR (1 B) + 3 reserved bytes – a 4-byte gap.

Mirrors the FSP ICU_IRQCR_CH(c) macro: for c in 16..31 the byte offset is c + 4 from IRQCRa[0] which lands inside IRQCRb after the 4-byte NMICR/reserved gap.

HUM Ch 14.2.12 "IRQCRi : IRQ Control Register", p 535

Parameters

[in]

irq_num

IRQ channel 0..31.

Returns

Volatile pointer to the IRQCR byte, or nullptr if out of range.

Definition at line 232 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, k_ra8_icu_irqcrb_first, k_ra8_icu_irqcrb_offset, k_ra8_icu_num_irqs, and k_ra8_icu_off_irqcra0.

Referenced by ra8_icu_configure_irq_pin(), ra8_icu_init(), and ra8_icu_read_irqcr().

ra8_icu_nmiclr()

volatile uint32_t * ra8_icu_nmiclr ( void )

inlinestatic

Get pointer to the 32-bit NMICLR register.

Definition at line 139 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_nmiclr.

Referenced by ra8_icu_init(), and ra8_icu_nmi_clear().

ra8_icu_nmicr()

volatile uint8_t * ra8_icu_nmicr ( void )

inlinestatic

Get pointer to the 8-bit NMICR register.

Definition at line 145 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_nmicr.

ra8_icu_nmier()

volatile uint32_t * ra8_icu_nmier ( void )

inlinestatic

Get pointer to the 32-bit NMIER register.

Definition at line 127 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_nmier.

Referenced by ra8_icu_init(), ra8_icu_nmi_disable(), and ra8_icu_nmi_enable().

ra8_icu_nmisr()

volatile uint32_t * ra8_icu_nmisr ( void )

inlinestatic

Get pointer to the 32-bit NMISR register.

Definition at line 133 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_nmisr.

Referenced by internal_nmi_report(), internal_ra8_board_nmi_report(), and ra8_icu_nmi_status().

ra8_icu_wupen0()

volatile uint32_t * ra8_icu_wupen0 ( void )

inlinestatic

Get pointer to the 32-bit WUPEN0 register.

WUPEN0 holds 16 IRQWUPENn bits (channels 0..15) at [15:0] and 16 peripheral WUPENn bits at [31:16]. HUM Ch 14 "WUPEN : Wake Up Interrupt Enable Register 0", p 524..582.

Definition at line 158 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_wupen0.

Referenced by ra8_icu_init().

ra8_icu_wupen1()

volatile uint32_t * ra8_icu_wupen1 ( void )

inlinestatic

Get pointer to the 32-bit WUPEN1 register.

WUPEN1 holds 16 peripheral WUPEN16..31 bits at [15:0] and 16 IRQWUPEN16..31 bits at [31:16]. HUM Ch 14 "WUPEN : Wake Up Interrupt Enable Register 1", p 524..582.

Definition at line 171 of file ra8_icu_regs.h.

References k_ra8_icu_base_addr, and k_ra8_icu_off_wupen1.

Referenced by ra8_icu_init().