main.c

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#include <stdint.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_check.h"
#include "ra8_dtc.h"
#include "ra8_dtc_regs.h"
#include "ra8_elc.h"
#include "ra8_err.h"
#include "ra8_icu_regs.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_time.h"

static const char* s_tag = "dtc_demo";

typedef enum : uint32_t {
  k_dtc_demo_baud       = 115200U, 
  k_dtc_demo_period_ms  = 1000U,   
  k_dtc_demo_buf_bytes  = 1024U,   
  k_dtc_demo_buf_words  = 256U,    
  k_dtc_demo_poll_limit = 200000U, 
} dtc_demo_config_t;

typedef enum : uint8_t {
  k_dtc_demo_byte_sh  = 8U,  
  k_dtc_demo_isr_prio = 12U, 
} dtc_demo_byte_t;

typedef enum : uint16_t {
  k_dtc_demo_event_swevt0 = 0x0CCU, 
} dtc_demo_event_t;

typedef enum : uint8_t {
  k_dtc_demo_swevt_index = 0U, 
} dtc_demo_swevt_t;

typedef enum : uint8_t {
  k_dtc_md_block = 0x2U, 
  k_dtc_sz_word  = 0x2U, 
  k_dtc_sm_inc   = 0x2U, 
  k_dtc_dm_inc   = 0x2U, 
} dtc_mr_field_t;

typedef enum : uint8_t {
  k_dtc_mra_md_pos   = 6U,  
  k_dtc_mra_sz_pos   = 4U,  
  k_dtc_mra_sm_pos   = 2U,  
  k_dtc_mrb_dm_pos   = 2U,  
  k_dtc_mra_byte_pos = 24U, 
  k_dtc_mrb_byte_pos = 16U, 
} dtc_mr_pos_t;

typedef enum : uint16_t {
  k_dtc_cra_block_256 = 0x0000U, 
  k_dtc_crb_one_block = 0x0001U, 
} dtc_count_t;

typedef enum : uint32_t {
  k_dtc_vt_entries = 96U,   
  k_dtc_vt_align   = 1024U, 
  k_dtc_ti_align   = 16U,   
} dtc_vt_geom_t;

typedef enum : uint32_t {
  k_dtc_cra_block_units = 256U, 
} dtc_cra_t;
 
static_assert((uint32_t)k_dtc_demo_buf_words == (uint32_t)k_dtc_cra_block_units,
              "CRA=0x0000 encodes a 256-unit block; buffer must be 256 words");

static const uint8_t k_dtc_demo_ok_msg[]  = "dtc: copied 1024B match=Y\r\n";
static const uint8_t k_dtc_demo_bad_msg[] = "dtc: copied 1024B match=N\r\n";

static uint32_t s_src[k_dtc_demo_buf_words];
static uint32_t s_dst[k_dtc_demo_buf_words];

[[gnu::aligned(k_dtc_vt_align)]] static uint32_t s_dtc_vt[k_dtc_vt_entries];

[[gnu::aligned(k_dtc_ti_align)]] static r_dtc_xfer_info_t s_dtc_ti;

static uint16_t s_dtc_slot;

volatile uint32_t g_dtc_match = 0U;

volatile uint32_t g_dtc_bytes = 0U;

volatile uint32_t g_dtc_activations = 0U;

volatile uint32_t g_dtc_isr_count = 0U;

volatile uint32_t g_dtc_heartbeat = 0U;

static void dtc_demo_panic_halt(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

static void dtc_demo_complete_cb(void* ctx, uint16_t status)
{
  (void)ctx;
  (void)status;
  ++g_dtc_isr_count;
}

static void dtc_demo_swevt_isr(void* ctx)
{
  (void)ctx;
  ra8_dtc_dispatch();
}

static void dtc_demo_setup_or_halt(void)
{
  uint32_t cpuclk0_hz = 0U;
 
  if (ra8_cgc_init() != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_cgc_get_clock_hz(k_ra8_clock_id_cpuclk0, &cpuclk0_hz) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_mstp_init() != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_isr_init() != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_elc_init() != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_board_uart_console_init((uint32_t)k_dtc_demo_baud) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_board_led_init(k_ra8_board_led2) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
}

static void dtc_demo_fill_buffers(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dtc_demo_buf_words; ++i) {
    s_src[i] = i ^ (i >> (uint32_t)k_dtc_demo_byte_sh);
    s_dst[i] = 0U;
  }
}

static void dtc_demo_program_ti(void)
{
  const uint8_t mra = (uint8_t)(((uint8_t)k_dtc_md_block << k_dtc_mra_md_pos) |
                                ((uint8_t)k_dtc_sz_word << k_dtc_mra_sz_pos) |
                                ((uint8_t)k_dtc_sm_inc << k_dtc_mra_sm_pos));
  const uint8_t mrb = (uint8_t)((uint8_t)k_dtc_dm_inc << k_dtc_mrb_dm_pos);
  /* MR[31:24]=MRA, MR[23:16]=MRB, MR[15:8]=MRC(0); HUM Ch 18.2.2 p 786 /
   * 18.2.3 p 787 / 18.2.4 p 789, Figure 18.4 p 799. SRAM (not MMIO). */
  s_dtc_ti.MR  = ((uint32_t)mra << k_dtc_mra_byte_pos) | ((uint32_t)mrb << k_dtc_mrb_byte_pos);
  s_dtc_ti.SAR = (uint32_t)(uintptr_t)s_src;
  s_dtc_ti.DAR = (uint32_t)(uintptr_t)s_dst;
  s_dtc_ti.CRB = (uint16_t)k_dtc_crb_one_block;
  s_dtc_ti.CRA = (uint16_t)k_dtc_cra_block_256;
}

[[nodiscard]] static ra8_err_t dtc_demo_arm_slot(void)
{
  volatile uint32_t* slot_reg = ra8_icu_ielsr(s_dtc_slot);
  if (slot_reg == nullptr) {
    return k_ra8_err_hw_error;
  }
  /* HUM Ch 14.2.17 "IELSRn : ICU Event Link Setting Register n" p 547:
   * DTCE[24] enables DTC activation; IR[16] is the RW1C status flag. */
  const uint32_t cur = *slot_reg;
  *slot_reg          = cur | (uint32_t)k_ra8_ielsr_dtce_mask;
  return k_ra8_ok;
}

static void dtc_demo_bringup_or_halt(void)
{
  if (ra8_dtc_init(s_dtc_vt) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_dtc_attach_handler(dtc_demo_complete_cb, nullptr) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (ra8_isr_register((ra8_elc_event_t)k_dtc_demo_event_swevt0,
                       dtc_demo_swevt_isr,
                       nullptr,
                       (uint8_t)k_dtc_demo_isr_prio,
                       &s_dtc_slot) != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
  if (s_dtc_slot >= (uint16_t)k_dtc_vt_entries) {
    dtc_demo_panic_halt();
  }
  /* DTCVBR + slot*4 holds the 16-byte-aligned TI start address; bit0 is
   * the privilege attribution (0 = privileged). HUM Ch 18.3.1 p 796 +
   * Figure 18.3 p 798. SRAM vector-table write (not MMIO). */
  s_dtc_vt[s_dtc_slot] = (uint32_t)(uintptr_t)&s_dtc_ti;
  if (ra8_dtc_enable() != k_ra8_ok) {
    dtc_demo_panic_halt();
  }
}

static uint8_t dtc_demo_verify(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dtc_demo_buf_words; ++i) {
    if (s_dst[i] != s_src[i]) {
      return 0U;
    }
  }
  return 1U;
}

[[nodiscard]] static ra8_err_t dtc_demo_run_once(uint8_t* out_ok)
{
  RA8_CHECK_NULL_PTR(out_ok, s_tag, "out_ok must not be nullptr");
 
  dtc_demo_program_ti();
  const ra8_err_t arm = dtc_demo_arm_slot();
  if (arm != k_ra8_ok) {
    return arm;
  }
  const ra8_err_t trig = ra8_elc_software_trigger((uint8_t)k_dtc_demo_swevt_index);
  if (trig != k_ra8_ok) {
    return trig;
  }
  ++g_dtc_activations;
 
  for (uint32_t i = 0U; i < (uint32_t)k_dtc_demo_poll_limit; ++i) {
    if (s_dst[k_dtc_demo_buf_words - 1U] == s_src[k_dtc_demo_buf_words - 1U]) {
      break;
    }
  }
 
  *out_ok = dtc_demo_verify();
  return k_ra8_ok;
}
 
void main(void)
{
  dtc_demo_setup_or_halt();
  dtc_demo_bringup_or_halt();
  /* Completion is detected by polling ``s_dst`` (step 4 below), so the global
   * interrupt is intentionally left masked. On RA8 silicon, enabling the
   * DTC-complete CPU interrupt lets its ISR (which writes ``DTCSTS``) race the
   * in-flight DTC transfer and corrupt the copy; the headless emulator, which
   * runs the transfer synchronously on the ELSEGR write, does not expose this.
   * The IELSR slot + ``DTCE`` armed in bring-up still activate the DTC -- we
   * simply do not take the completion IRQ. */
 
  while (1) {
    dtc_demo_fill_buffers();
    uint8_t         ok   = 0U;
    const ra8_err_t err  = dtc_demo_run_once(&ok);
    const uint8_t   good = (err == k_ra8_ok && ok != 0U) ? 1U : 0U;
    g_dtc_match          = (uint32_t)good;
    g_dtc_bytes          = (good != 0U) ? (uint32_t)k_dtc_demo_buf_bytes : 0U;
    if (good != 0U) {
      (void)ra8_board_uart_console_write(k_dtc_demo_ok_msg,
                                         (size_t)(sizeof(k_dtc_demo_ok_msg) - 1U));
      (void)ra8_board_led_toggle(k_ra8_board_led1);
    } else {
      (void)ra8_board_uart_console_write(k_dtc_demo_bad_msg,
                                         (size_t)(sizeof(k_dtc_demo_bad_msg) - 1U));
      (void)ra8_board_led_toggle(k_ra8_board_led2);
    }
    ++g_dtc_heartbeat;
    ra8_delay_ms(k_dtc_demo_period_ms);
  }
  dtc_demo_panic_halt();
}