ra8_icu_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
/* =============================================================================
 * Base addresses
 * =============================================================================
 */
 
typedef enum : uintptr_t {
  k_ra8_icu_base_addr = 0x40006000UL, 
} ra8_icu_addr_t;
 
typedef enum : uint16_t {
  k_ra8_icu_num_ielsr     = 96U, 
  k_ra8_icu_num_irqs      = 32U, 
  k_ra8_icu_irqcra_count  = 16U, 
  k_ra8_icu_irqcrb_first  = 16U, 
  k_ra8_icu_irqcrb_offset = 4U,  
} ra8_icu_limits_t;
 
/* =============================================================================
 * Register offsets (verified against FSP R_ICU_Type in
 * R7KA8D2KF_core0.h lines 8670-9061)
 * =============================================================================
 */
 
typedef enum : uint32_t {
  k_ra8_icu_off_irqcra0 = 0x0000U, 
  k_ra8_icu_off_nmicr   = 0x0010U, 
  k_ra8_icu_off_irqcrb0 = 0x0014U, 
  k_ra8_icu_off_intselr = 0x0040U, 
  k_ra8_icu_off_nmier   = 0x6100U, 
  k_ra8_icu_off_nmiclr  = 0x6110U, 
  k_ra8_icu_off_nmisr   = 0x6120U, 
  k_ra8_icu_off_wupen0  = 0x61A0U, 
  k_ra8_icu_off_wupen1  = 0x61A4U, 
  k_ra8_icu_off_dslpwup = 0x6210U, 
  k_ra8_icu_off_delsr0  = 0x6280U, 
  k_ra8_icu_off_ielsr0  = 0x6300U, 
} ra8_icu_off_t;

typedef enum : uint8_t {
  k_ra8_icu_irqmd_falling = 0U, 
  k_ra8_icu_irqmd_rising  = 1U, 
  k_ra8_icu_irqmd_both    = 2U, 
  k_ra8_icu_irqmd_low     = 3U, 
} ra8_icu_irqmd_t;

typedef enum : uint8_t {
  k_ra8_icu_fclksel_pclkb    = 0U, 
  k_ra8_icu_fclksel_pclkb_8  = 1U, 
  k_ra8_icu_fclksel_pclkb_32 = 2U, 
  k_ra8_icu_fclksel_pclkb_64 = 3U, 
} ra8_icu_fclksel_t;

typedef enum : uint8_t {
  k_ra8_icu_irqcr_bit_fclksel = 4U, 
  k_ra8_icu_irqcr_bit_flten   = 7U, 
} ra8_icu_irqcr_bit_t;

typedef enum : uint8_t {
  k_ra8_icu_irqcr_mask_irqmd   = 0x03U, 
  k_ra8_icu_irqcr_mask_fclksel = 0x30U, 
  k_ra8_icu_irqcr_mask_flten   = 0x80U, 
} ra8_icu_irqcr_mask_t;

static inline volatile uint32_t* ra8_icu_nmier(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_nmier);
}

static inline volatile uint32_t* ra8_icu_nmisr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_nmisr);
}

static inline volatile uint32_t* ra8_icu_nmiclr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_nmiclr);
}

static inline volatile uint8_t* ra8_icu_nmicr(void)
{
  return (volatile uint8_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_nmicr);
}

static inline volatile uint32_t* ra8_icu_wupen0(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_wupen0);
}

static inline volatile uint32_t* ra8_icu_wupen1(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_wupen1);
}

static inline volatile uint32_t* ra8_icu_delsr(uint8_t index)
{
  enum ra8_icu_delsr_bound : uint8_t {
    k_ra8_icu_num_delsr = 8U, 
  };
  if (index >= k_ra8_icu_num_delsr) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_delsr0 +
                              ((uintptr_t)index * sizeof(uint32_t)));
}
 
/* =============================================================================
 * Accessors
 * =============================================================================
 */

static inline volatile uint32_t* ra8_icu_ielsr(uint16_t index)
{
  if (index >= k_ra8_icu_num_ielsr) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_ielsr0 +
                              ((uintptr_t)index * sizeof(uint32_t)));
}

static inline volatile uint8_t* ra8_icu_irqcr(uint8_t irq_num)
{
  if (irq_num >= (uint8_t)k_ra8_icu_num_irqs) {
    return nullptr;
  }
  /* HUM Ch 14.2.12 "IRQCRi : IRQ Control Register", p 535: IRQCRa
   * occupies bytes 0..15, NMICR + reserved fill 16..19, IRQCRb starts
   * at 20.  Match FSP ICU_IRQCR_CH(c) = c + ((c >> 4) << 2). */
  const uintptr_t gap_bytes = ((uintptr_t)irq_num >= (uintptr_t)k_ra8_icu_irqcrb_first)
                                ? (uintptr_t)k_ra8_icu_irqcrb_offset
                                : (uintptr_t)0U;
  return (volatile uint8_t*)((uintptr_t)k_ra8_icu_base_addr + (uintptr_t)k_ra8_icu_off_irqcra0 +
                             (uintptr_t)irq_num + gap_bytes);
}
 
/* =============================================================================
 * IELSR bit layout
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_ielsr_iels_shift = 0U,  
  k_ra8_ielsr_ir_bit     = 16U, 
  k_ra8_ielsr_dtce_bit   = 24U, 
} ra8_ielsr_bit_t;
 
typedef enum : uint32_t {
  /* HUM Ch 14.2.17 "IELSRn : ICU Event Link Setting Register n", p 547:
   * IELS occupies bits [9:0] -- 10-bit field, mask 0x3FF.  RA8 has
   * hundreds of ELC event sources so the FSP layout uses 10 bits. */
  k_ra8_ielsr_iels_mask = 0x000003FFUL, 
  k_ra8_ielsr_ir_mask   = 0x00010000UL, 
  k_ra8_ielsr_dtce_mask = 0x01000000UL, 
} ra8_ielsr_mask_t;
 
#ifdef __cplusplus
}
#endif