DTC arm/disarm demo built on the ra8_isr_set_dtc() HAL primitive. More...

#include <stdint.h>
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_check.h"
#include "ra8_dtc.h"
#include "ra8_dtc_regs.h"
#include "ra8_elc.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_mstp.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Enumerations
enum	dtc_arm_config_t : uint32_t { k_dtc_arm_baud = 115200U , k_dtc_arm_period_ms = 1000U , k_dtc_arm_buf_bytes = 1024U , k_dtc_arm_buf_words = 256U , k_dtc_arm_poll_limit = 200000U , k_dtc_arm_settle = 20000U , k_dtc_arm_dst_sentinel = 0xA5A5A5A5U }
	Compile-time settings. More...
enum	dtc_arm_byte_t : uint8_t { k_dtc_arm_byte_sh = 8U , k_dtc_arm_isr_prio = 12U }
	Single-byte constants. More...
enum	dtc_arm_event_t : uint16_t { k_dtc_arm_event_swevt0 = 0x0CCU }
	ELC software event 0 -> ICU event number. More...
enum	dtc_arm_swevt_t : uint8_t { k_dtc_arm_swevt_index = 0U }
	ELSEGRn index fired by ra8_elc_software_trigger. More...
enum	dtc_arm_mr_field_t : uint8_t { k_dtc_arm_md_block = 0x2U , k_dtc_arm_sz_word = 0x2U , k_dtc_arm_sm_inc = 0x2U , k_dtc_arm_dm_inc = 0x2U }
	DTC Transfer-Information mode-bit field values. More...
enum	dtc_arm_mr_pos_t : uint8_t { k_dtc_arm_mra_md_pos = 6U , k_dtc_arm_mra_sz_pos = 4U , k_dtc_arm_mra_sm_pos = 2U , k_dtc_arm_mrb_dm_pos = 2U , k_dtc_arm_mra_byte_pos = 24U , k_dtc_arm_mrb_byte_pos = 16U }
	Bit positions inside the DTC TI MR word. More...
enum	dtc_arm_count_t : uint16_t { k_dtc_arm_cra_block_256 = 0x0000U , k_dtc_arm_crb_one_block = 0x0001U }
	DTC count-register values for one 256-word block. More...
enum	dtc_arm_vt_geom_t : uint32_t { k_dtc_arm_vt_entries = 96U , k_dtc_arm_vt_align = 1024U , k_dtc_arm_ti_align = 16U }
	DTC vector-table geometry. More...
enum	dtc_arm_cra_t : uint32_t { k_dtc_arm_cra_block_units = 256U }
	CRA=0x0000 encodes a full 256-unit block. More...

Functions
static void	dtc_arm_panic_halt (void)
	Park forever after a fatal init failure.
static void	dtc_arm_complete_cb (void *ctx, uint16_t status)
	DTC completion callback (fanned out by ra8_dtc_dispatch).
static void	dtc_arm_swevt_isr (void *ctx)
	IELSR-slot ISR for the DTC-complete interrupt.
static void	dtc_arm_setup_or_halt (void)
	Bring CGC + SysTick + ISR + ELC + SCI8 + LEDs + MSTP up.
static void	dtc_arm_fill (uint32_t dst_init)
	Fill s_src with a deterministic pattern and s_dst with a value.
static void	dtc_arm_program_ti (void)
	Write the 16-byte TI block describing the block copy.
static void	dtc_arm_bringup_or_halt (void)
	Initialise the DTC, allocate its activation slot, and enable it.
static uint8_t	dtc_arm_all_match_src (void)
	Verify s_dst matches s_src element-by-element.
static uint8_t	dtc_arm_all_equal (uint32_t expect)
	Verify every word of s_dst still holds expect.
static ra8_err_t	dtc_arm_run_armed (uint8_t *out_ok)
	Run one ARMED pass: DTCE = 1, fire the event, expect a full copy.
static ra8_err_t	dtc_arm_run_disarmed (uint8_t *out_ok)
	Run one DISARMED pass: DTCE = 0, fire the event, expect NO copy.
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
static const char *	s_tag = "dtc_arm"
	Diagnostic / log tag.
static const uint8_t	k_dtc_arm_ok_msg [] = "dtc-arm: armed+disarmed OK\r\n"
	Output line tags.
static const uint8_t	k_dtc_arm_bad_msg [] = "dtc-arm: FAILED\r\n"
static uint32_t	s_src [k_dtc_arm_buf_words]
	Source / destination buffers (32-bit aligned by element type).
static uint32_t	s_dst [k_dtc_arm_buf_words]
static uint32_t	s_dtc_vt [k_dtc_arm_vt_entries]
	DTC vector table – one 4-byte TI start address per IELSR slot.
static r_dtc_xfer_info_t	s_dtc_ti
	The 16-byte Transfer Information block the DTC reads each pass.
static uint16_t	s_dtc_slot
	IELSR slot allocated for the DTC activation = DTC vector number.
volatile uint32_t	g_dtc_armed_ok = 0U
	1 when the armed pass copied the block correctly.
volatile uint32_t	g_dtc_disarmed_ok = 0U
	1 when the disarmed pass left the destination untouched.
volatile uint32_t	g_dtc_activations = 0U
	Count of ELC software-event triggers issued (armed + disarmed).
volatile uint32_t	g_dtc_isr_count = 0U
	Count of DTC-complete callbacks fanned through the HAL dispatch.
volatile uint32_t	g_dtc_heartbeat = 0U
	Bumps once per main-loop pass – liveness for headless probes.

Detailed Description

DTC arm/disarm demo built on the ra8_isr_set_dtc() HAL primitive.

Tag: [Ring 6 / APP] {World: S}

The DTC counterpart to dtc_transfer_demo – same 1 KB SRAM-to-SRAM block copy, same ELC-software-event activation – but it arms and disarms DTC activation through the ra8_isr_set_dtc() HAL primitive (issue #579) instead of open-coding the ICU.IELSRn.DTCE read-modify-write. Because the primitive owns that write, this app never includes ra8_icu_regs.h at all: the DTC-vs-CPU routing decision for the allocated slot no longer leaks into application code.

Once a second the loop runs two phases and reports whether BOTH matched their expectation:

Armed. Fill a 1 KB source with a deterministic pattern (i ^ (i >> 8)), zero the destination, program the Transfer Information block, ra8_isr_set_dtc(slot, true), then fire ELC software event 0. The DTC activates and copies the block; the destination must equal the source.
Disarmed. Refill the destination with a sentinel (0xA5A5A5A5), reprogram the TI, ra8_isr_set_dtc(slot, false), then fire the same event again. With DTCE clear the DTC does not activate, so the destination must still be entirely the sentinel – proof that clearing DTCE truly gates the transfer.

good = armed_ok && disarmed_ok gates the banner "dtc-arm: armed+disarmed OK\r\n" on the J-Link OB CDC channel; any failure prints "dtc-arm: FAILED\r\n". LED1 toggles on success, LED2 on failure, and the g_dtc_* globals mirror the result for headless probing (HIL / board emulator).

Bare EK-RA8D2 only – no shields or external transceivers.

Note: Headless-emulator status. tools/ra8_emulator models the DTC descriptor engine (board_periph_dtc.c) AND its DTCE gate: the ELC software event activates the controller only when a DTCE-enabled IELSR slot links the event, so the armed phase copies and the disarmed phase leaves the sentinel intact – the same match the banner reports. Not yet confirmed on silicon; the DTC activation path is byte-identical to the silicon-validated dtc_transfer_demo (the primitive performs the exact same IELSRn.DTCE write), so promotion to hw_validated/hil/ needs only a bench run. See README.md.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file main.c.

Enumeration Type Documentation

◆ dtc_arm_byte_t

enum dtc_arm_byte_t : uint8_t

Single-byte constants.

Enumerator
k_dtc_arm_byte_sh	Source-pattern shift (i ^ (i >> 8)).
k_dtc_arm_isr_prio	NVIC priority for the DTC-complete slot.

Definition at line 84 of file main.c.

◆ dtc_arm_config_t

enum dtc_arm_config_t : uint32_t

Compile-time settings.

Enumerator
k_dtc_arm_baud	SCI8 baud rate.
k_dtc_arm_period_ms	Delay between passes.
k_dtc_arm_buf_bytes	Bytes copied per armed pass.
k_dtc_arm_buf_words	32-bit words per buffer / block.
k_dtc_arm_poll_limit	Bounded wait for the block to land.
k_dtc_arm_settle	Bounded settle for the disarmed pass.
k_dtc_arm_dst_sentinel	Disarmed-phase destination fill.

Definition at line 73 of file main.c.

◆ dtc_arm_count_t

enum dtc_arm_count_t : uint16_t

DTC count-register values for one 256-word block.

HUM Ch 18.2.7 "CRA" (p 790): in block mode CRAH/CRAL hold the block size and "the transfer count is ... 256 when the set value is 0x00". HUM Ch 18.2.8 "CRB" (p 791): CRB is the block count.

Enumerator
k_dtc_arm_cra_block_256	CRAH = CRAL = 0 => 256-unit block.
k_dtc_arm_crb_one_block	CRB = 1 => one block per pass.

Definition at line 147 of file main.c.

◆ dtc_arm_cra_t

enum dtc_arm_cra_t : uint32_t

CRA=0x0000 encodes a full 256-unit block.

Enumerator
k_dtc_arm_cra_block_units	Units per block when CRAH/CRAL = 0.

Definition at line 169 of file main.c.

◆ dtc_arm_event_t

enum dtc_arm_event_t : uint16_t

ELC software event 0 -> ICU event number.

HUM Table 19.3 (p 824) row "0x0CC | ELC | ELC_SWEVT0 | Software event 0": ra8_elc_software_trigger(0) writes ELSEGR0.SEG which raises this event; routed to an IELSR slot with DTCE = 1 it activates the DTC. App local (the shared ra8_elc_event_t table only carries events the HAL itself wires), mirroring dtc_transfer_demo.

Enumerator
k_dtc_arm_event_swevt0	ELC software event 0 (HUM Table 19.3).

Definition at line 99 of file main.c.

◆ dtc_arm_mr_field_t

enum dtc_arm_mr_field_t : uint8_t

DTC Transfer-Information mode-bit field values.

HUM Ch 18.2.2 "MRA" (p 786) and 18.2.3 "MRB" (p 787): a block-mode, 32-bit-word, increment-both copy. 2 selects "increment" for SM/DM, "32-bit word" for SZ, and "block transfer" for MD.

Enumerator
k_dtc_arm_md_block	MRA.MD[7:6] = 10b: block transfer mode.
k_dtc_arm_sz_word	MRA.SZ[5:4] = 10b: 32-bit word units.
k_dtc_arm_sm_inc	MRA.SM[3:2] = 10b: increment SAR.
k_dtc_arm_dm_inc	MRB.DM[3:2] = 10b: increment DAR.

Definition at line 116 of file main.c.

◆ dtc_arm_mr_pos_t

enum dtc_arm_mr_pos_t : uint8_t

Bit positions inside the DTC TI MR word.

HUM Figure 18.4 (p 799) lays the first TI long-word out as MR[31:24] = MRA, MR[23:16] = MRB, MR[15:8] = MRC, MR[7:0] = reserved.

Enumerator
k_dtc_arm_mra_md_pos	MRA.MD field position.
k_dtc_arm_mra_sz_pos	MRA.SZ field position.
k_dtc_arm_mra_sm_pos	MRA.SM field position.
k_dtc_arm_mrb_dm_pos	MRB.DM field position.
k_dtc_arm_mra_byte_pos	MRA byte offset within MR.
k_dtc_arm_mrb_byte_pos	MRB byte offset within MR.

Definition at line 130 of file main.c.

◆ dtc_arm_swevt_t

enum dtc_arm_swevt_t : uint8_t

ELSEGRn index fired by ra8_elc_software_trigger.

Enumerator
k_dtc_arm_swevt_index	ELSEGR0 -> ELC_SWEVT0 (0x0CC).

Definition at line 104 of file main.c.

◆ dtc_arm_vt_geom_t

enum dtc_arm_vt_geom_t : uint32_t

DTC vector-table geometry.

HUM Ch 18.3.1 (p 796) + Figure 18.3 (p 798): DTCVBR points at a table of 4-byte entries, one per interrupt vector number; entry n (at DTCVBR + n*4) holds the 16-byte-aligned start address of that source's TI. DTCVBR itself must be 1 KB-aligned (HUM Ch 18.2.11 p 792 "the lower 10 bits should be 0").

Enumerator
k_dtc_arm_vt_entries	One pointer per IELSR slot 0..95.
k_dtc_arm_vt_align	DTCVBR 1 KB alignment (HUM 18.2.11).
k_dtc_arm_ti_align	TI start address multiple of 16.

Definition at line 162 of file main.c.

Function Documentation

◆ dtc_arm_all_equal()

uint8_t dtc_arm_all_equal ( uint32_t expect )

static

Verify every word of s_dst still holds expect.

MC/DC:: Compound decision in the loop: s_dst[i] != expect. One atomic condition x 2 vectors – untouched (disarmed steady-state) and one differing word (a DTC that wrongly ran with DTCE clear).

Parameters

[in] expect Value every destination word must still hold.

Returns: 1 if every word equals expect, 0 otherwise.

Precondition: s_dst was filled with expect before the pass.

Postcondition: Return value is 0 or 1.

Since: 0.1.0

Definition at line 449 of file main.c.

References k_dtc_arm_buf_words, and s_dst.

Referenced by dtc_arm_run_disarmed().

◆ dtc_arm_all_match_src()

uint8_t dtc_arm_all_match_src ( void )

static

Verify s_dst matches s_src element-by-element.

MC/DC:: Compound decision in the loop: s_dst[i] != s_src[i]. One atomic condition x 2 vectors – match (armed steady-state) and one mismatch (covered by the headless emulator, which never runs the transfer).

Returns: 1 if all elements equal, 0 otherwise.

Precondition: Buffers are filled.

Postcondition: Return value is 0 or 1.

Since: 0.1.0

Definition at line 425 of file main.c.

References k_dtc_arm_buf_words, s_dst, and s_src.

Referenced by dtc_arm_run_armed().

◆ dtc_arm_bringup_or_halt()

void dtc_arm_bringup_or_halt ( void )

static

Initialise the DTC, allocate its activation slot, and enable it.

Programs DTCVBR to s_dtc_vt, attaches the completion callback, allocates an IELSR slot for ELC software event 0 (whose index is the DTC vector number), points that slot's vector-table entry at the TI block, and starts the engine (DTCST = 1). Halts on any failure.

Precondition: ra8_isr_init / ra8_elc_init have run; IRQs not yet enabled.

Postcondition: The DTC is enabled and s_dtc_vt[s_dtc_slot] points at the TI.

Since: 0.1.0

Definition at line 385 of file main.c.

References dtc_arm_complete_cb(), dtc_arm_panic_halt(), dtc_arm_swevt_isr(), k_dtc_arm_event_swevt0, k_dtc_arm_isr_prio, k_dtc_arm_vt_entries, k_ra8_ok, ra8_dtc_attach_handler(), ra8_dtc_enable(), ra8_dtc_init(), ra8_isr_register(), s_dtc_slot, s_dtc_ti, and s_dtc_vt.

Referenced by main().

◆ dtc_arm_complete_cb()

void dtc_arm_complete_cb	(	void *	ctx,
		uint16_t	status )

static

DTC completion callback (fanned out by ra8_dtc_dispatch).

Parameters

[in]	ctx	Unused registration context.
[in]	status	DTCSTS snapshot at completion.

Precondition: Attached via ra8_dtc_attach_handler.

Postcondition: g_dtc_isr_count incremented once.

Note: ISR context; not re-entrant.

Since: 0.1.0

Definition at line 259 of file main.c.

References g_dtc_isr_count.

Referenced by dtc_arm_bringup_or_halt().

◆ dtc_arm_fill()

void dtc_arm_fill ( uint32_t dst_init )

static

Fill s_src with a deterministic pattern and s_dst with a value.

MC/DC:: Trivial loop with no compound decision – only the implicit loop exit condition. No N+1 vectors required.

Parameters

[in] dst_init Value written to every destination word before a pass.

Precondition: Buffers are statically allocated.

Postcondition: Every word in s_src is set; s_dst is all dst_init.

Since: 0.1.0

Definition at line 332 of file main.c.

References k_dtc_arm_buf_words, k_dtc_arm_byte_sh, s_dst, and s_src.

Referenced by dtc_arm_run_armed(), and dtc_arm_run_disarmed().

◆ dtc_arm_panic_halt()

void dtc_arm_panic_halt ( void )

static

Park forever after a fatal init failure.

Definition at line 242 of file main.c.

Referenced by dtc_arm_bringup_or_halt(), and dtc_arm_setup_or_halt().

◆ dtc_arm_program_ti()

void dtc_arm_program_ti ( void )

static

Write the 16-byte TI block describing the block copy.

Rebuilt every pass because the DTC writes the post-transfer TI back to SRAM (MRA.WBDIS = 0, HUM Ch 18.2.2 p 786), consuming SAR/DAR/CRA/CRB. Field encoding per HUM Figure 18.4 (p 799): MR holds MRA/MRB/MRC, then SAR, DAR, CRB, CRA.

MC/DC:: Straight-line assignment – no decision points.

Precondition: s_src / s_dst are populated.

Postcondition: s_dtc_ti describes a 256-word, 32-bit, increment-both copy.

Since: 0.1.0

Definition at line 356 of file main.c.

References k_dtc_arm_cra_block_256, k_dtc_arm_crb_one_block, k_dtc_arm_dm_inc, k_dtc_arm_md_block, k_dtc_arm_mra_byte_pos, k_dtc_arm_mra_md_pos, k_dtc_arm_mra_sm_pos, k_dtc_arm_mra_sz_pos, k_dtc_arm_mrb_byte_pos, k_dtc_arm_mrb_dm_pos, k_dtc_arm_sm_inc, k_dtc_arm_sz_word, s_dst, s_dtc_ti, and s_src.

Referenced by dtc_arm_run_armed(), and dtc_arm_run_disarmed().

◆ dtc_arm_run_armed()

ra8_err_t dtc_arm_run_armed ( uint8_t * out_ok )

staticnodiscard

Run one ARMED pass: DTCE = 1, fire the event, expect a full copy.

Zeroes the destination, rebuilds the TI, arms the slot via ra8_isr_set_dtc(s_dtc_slot, true), fires ELC software event 0, polls (bounded) for the last destination word to land, and reports whether the whole buffer copied.

Parameters

[out] out_ok 1 if the destination matched the source, else 0.

Returns: k_ra8_ok once the (bounded) attempt finishes, or the error from arming the slot / firing the software event.

Return values

k_ra8_ok	The pass completed (see *out_ok).
k_ra8_err_null_ptr	out_ok was NULL.

Precondition: The DTC is enabled and s_dtc_slot is registered.

Postcondition: *out_ok reflects the post-copy comparison.

Since: 0.1.0

Definition at line 477 of file main.c.

References dtc_arm_all_match_src(), dtc_arm_fill(), dtc_arm_program_ti(), g_dtc_activations, k_dtc_arm_buf_words, k_dtc_arm_poll_limit, k_dtc_arm_swevt_index, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_elc_software_trigger(), ra8_isr_set_dtc(), s_dst, s_dtc_slot, s_src, and s_tag.

Referenced by main().

◆ dtc_arm_run_disarmed()

ra8_err_t dtc_arm_run_disarmed ( uint8_t * out_ok )

staticnodiscard

Run one DISARMED pass: DTCE = 0, fire the event, expect NO copy.

Fills the destination with the sentinel, rebuilds the TI, disarms the slot via ra8_isr_set_dtc(s_dtc_slot, false), fires the same ELC software event, waits a bounded settle window, and reports whether the destination is still entirely the sentinel – proof the cleared DTCE gated the DTC.

Parameters

[out] out_ok 1 if the destination was untouched, else 0.

Returns: k_ra8_ok once the (bounded) attempt finishes, or the error from disarming the slot / firing the software event.

Return values

k_ra8_ok	The pass completed (see *out_ok).
k_ra8_err_null_ptr	out_ok was NULL.

Precondition: The DTC is enabled and s_dtc_slot is registered.

Postcondition: *out_ok reflects the untouched-destination check.

Since: 0.1.0

Definition at line 521 of file main.c.

References dtc_arm_all_equal(), dtc_arm_fill(), dtc_arm_program_ti(), g_dtc_activations, k_dtc_arm_buf_words, k_dtc_arm_dst_sentinel, k_dtc_arm_settle, k_dtc_arm_swevt_index, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_elc_software_trigger(), ra8_isr_set_dtc(), s_dst, s_dtc_slot, and s_tag.

Referenced by main().

◆ dtc_arm_setup_or_halt()

void dtc_arm_setup_or_halt ( void )

static

Bring CGC + SysTick + ISR + ELC + SCI8 + LEDs + MSTP up.

Definition at line 287 of file main.c.

References dtc_arm_panic_halt(), k_dtc_arm_baud, k_ra8_board_led1, k_ra8_board_led2, k_ra8_clock_id_cpuclk0, k_ra8_ok, ra8_board_led_init(), ra8_board_uart_console_init(), ra8_cgc_get_clock_hz(), ra8_cgc_init(), ra8_elc_init(), ra8_isr_init(), ra8_mstp_init(), and ra8_time_init().

Referenced by main().

◆ dtc_arm_swevt_isr()

void dtc_arm_swevt_isr ( void * ctx )

static

IELSR-slot ISR for the DTC-complete interrupt.

When the single block finishes, the DTC clears ICU.IELSRn.DTCE and raises the slot's CPU interrupt (HUM Figure 18.5 p 801). This routes the event through the HAL dispatch into dtc_arm_complete_cb.

Parameters

[in] ctx Unused registration context.

Precondition: Registered via ra8_isr_register for ELC software event 0.

Postcondition: ra8_dtc_dispatch has run exactly once.

Note: ISR context; not re-entrant.

Since: 0.1.0

Definition at line 280 of file main.c.

References ra8_dtc_dispatch().

Referenced by dtc_arm_bringup_or_halt().

◆ main()

void main ( void )

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has configured the clock tree and VTOR.

Postcondition: Control does not return; the image runs until reset or halt.; Any value the application wanted to report has been logged, not returned.

Note: Not thread-safe; single-threaded startup context only.

Warning: Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also: SystemInit()

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the playback loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the sweep loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.

Postcondition: On clean entry the kernel runs the worker thread once.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the kernel runs the worker thread forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition: Reset_Handler has copied .data + zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: CPUCLK0 is raised to the PLL1 target before the kernel starts.; On clean entry the SD card thread runs forever.; On any HAL init failure the function halts in __WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the iso-IN feed loop forever.; On any HAL init failure the function halts in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition: Boot init has completed.; The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition: Diagnostic counter latched, CPU parked in a halt loop.; Function never returns.

Note: Single-threaded entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.; On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.; On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition: The shelf scans on the panel; taps open books, browse, and read.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: On success the cache globals are latched and g_pc_heartbeat advances.; On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On clean entry the CPU stays in the profile + blink loop.; On any HAL hard error LED2 latches ON.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler has copied .data and zeroed .bss.; The shared board boot files installed the vector table.

Postcondition: The demo has run once and its verdict banner is streaming steadily.; The CPU idles re-emitting the banner (or halts after a fatal init error).

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit has set VTOR, FPU, and priority grouping.

Postcondition: On a clean run the CPU loops forever after the PASS banner.; On any failure the function prints FAIL and halts in WFI.

Note: Not thread-safe; this is the single-threaded app entry.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition: SystemInit configured VTOR / FPU / priority grouping.; The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition: Exactly one PASS or FAIL verdict line has been queued on SCI8.; Control parks in an infinite loop; the function never returns.

Note: Single-threaded; runs to the park loop on the main stack.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The cal=OK / cal=SKIP result and the finger-free touchcal: ready sentinel are emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR / FPU / priority grouping.

Postcondition: The open=OK touch banner is emitted; the CPU then loops in WFI.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Both USB controllers' clocks and pins come up before the kernel so the workers only deal with stack bring-up.

Precondition: Reset_Handler copied .data and zeroed .bss.; SystemInit set VTOR, FPU, priority grouping.

Postcondition: On clean entry the CPU stays in tx_kernel_enter forever.; On any HAL init failure the function halts in WFI.

Note: Single entry point; not re-entrant.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging and the clock tree, releases the Cortex-M33 (which then blinks LED1 via ra8_pcntr_set_output()), and idles. See the file header.

Precondition: SystemInit has completed core bring-up.; The M33 is held in reset by hardware until released here.

Postcondition: The M33 has been released and is blinking LED1.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Precondition: The application links ra8_c6link and ESP-hosted generated codecs.; No hardware validation is inferred from this function.

Postcondition: No c6link operation is attempted.; No network or storage state is modified.

Note: Single-threaded compile fixture.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Brings up logging, the clock tree, and the VCOM console, runs the cacheable-SRAM round-trip with the D-cache that SystemInit() enabled through ra8_cache_dcache_enable(), emits the matching PASS / FAIL banner over the console and ra8_log, then parks in WFI. Every byte the self-test touches runs with the L1 caches + MPU enabled by the shared boot (RA8_BOOT_ENABLE_CACHE_MPU + RA8_BOOT_CACHE_VIA_HAL).

Precondition: Reset_Handler has copied .data and zeroed .bss.; SystemInit enabled the MPU + I-cache + D-cache via the ra8_cache HAL.

Postcondition: Exactly one banner (PASS or FAIL) has been emitted.; The core is parked in WFI.

Note: Single-threaded; no RTOS and no IRQ sources in this template.

Since: 0.1.0

The application entry point Reset_Handler hands control to.

Publishes the mailbox, releases the Cortex-M33 into the emitter, yields until it signals done, validates the blob the M33 built, then logs the PASS/FAIL verdict and the chapter count read back from the blob. See the file header for the offload narrative.

Precondition: SystemInit has completed core bring-up.; The M33 is held inactive by hardware until released here.

Postcondition: The M33 has built a RABOOK1 blob and the M85 has validated it.; This function never returns to its caller.

Note: Single-threaded; no RTOS on the M85 in this example.

Since: 0.1.0

Definition at line 550 of file main.c.

References dtc_arm_bringup_or_halt(), dtc_arm_run_armed(), dtc_arm_run_disarmed(), dtc_arm_setup_or_halt(), g_dtc_armed_ok, g_dtc_disarmed_ok, g_dtc_heartbeat, k_dtc_arm_bad_msg, k_dtc_arm_ok_msg, k_dtc_arm_period_ms, k_ra8_board_led1, k_ra8_board_led2, k_ra8_ok, ra8_board_led_toggle(), ra8_board_uart_console_write(), and ra8_delay_ms().

Variable Documentation

◆ g_dtc_activations

volatile uint32_t g_dtc_activations = 0U

Count of ELC software-event triggers issued (armed + disarmed).

Count of ELC software-event triggers issued.

Note: Read externally only.

Since: 0.1.0

Definition at line 223 of file main.c.

Referenced by dtc_arm_run_armed(), dtc_arm_run_disarmed(), and dtc_demo_run_once().

◆ g_dtc_armed_ok

volatile uint32_t g_dtc_armed_ok = 0U

1 when the armed pass copied the block correctly.

Note: Read externally only (HIL / board emulator).

Since: 0.1.0

Definition at line 207 of file main.c.

Referenced by main().

◆ g_dtc_disarmed_ok

volatile uint32_t g_dtc_disarmed_ok = 0U

1 when the disarmed pass left the destination untouched.

Note: Read externally only.

Since: 0.1.0

Definition at line 215 of file main.c.

Referenced by main().

◆ g_dtc_heartbeat

volatile uint32_t g_dtc_heartbeat = 0U

Bumps once per main-loop pass – liveness for headless probes.

Note: Read externally only.

Since: 0.1.0

Definition at line 239 of file main.c.

Referenced by main().

◆ g_dtc_isr_count

volatile uint32_t g_dtc_isr_count = 0U

Count of DTC-complete callbacks fanned through the HAL dispatch.

Count of DTC-complete interrupts fanned through the HAL dispatch.

Note: Read externally only.

Since: 0.1.0

Definition at line 231 of file main.c.

Referenced by dtc_arm_complete_cb(), and dtc_demo_complete_cb().

◆ k_dtc_arm_bad_msg

const uint8_t k_dtc_arm_bad_msg[] = "dtc-arm: FAILED\r\n"

static

Definition at line 178 of file main.c.

Referenced by main().

◆ k_dtc_arm_ok_msg

const uint8_t k_dtc_arm_ok_msg[] = "dtc-arm: armed+disarmed OK\r\n"

static

Output line tags.

Definition at line 177 of file main.c.

Referenced by main().

◆ s_dst

uint32_t s_dst[k_dtc_arm_buf_words]

static

Definition at line 182 of file main.c.

Referenced by dtc_arm_all_equal(), dtc_arm_all_match_src(), dtc_arm_fill(), dtc_arm_program_ti(), dtc_arm_run_armed(), dtc_arm_run_disarmed(), dtc_coh_fill_buffers(), dtc_coh_program_ti(), dtc_coh_run_once(), dtc_coh_verify(), dtc_demo_fill_buffers(), dtc_demo_program_ti(), dtc_demo_run_once(), dtc_demo_verify(), internal_fill_buffers(), internal_run_copy(), and internal_verify().

◆ s_dtc_slot

uint16_t s_dtc_slot

static

IELSR slot allocated for the DTC activation = DTC vector number.

Definition at line 199 of file main.c.

Referenced by dtc_arm_bringup_or_halt(), dtc_arm_run_armed(), dtc_arm_run_disarmed(), dtc_coh_arm_slot(), dtc_coh_bringup_or_halt(), dtc_coh_program_ti(), dtc_demo_arm_slot(), and dtc_demo_bringup_or_halt().

◆ s_dtc_ti

r_dtc_xfer_info_t s_dtc_ti

static

The 16-byte Transfer Information block the DTC reads each pass.

Warning: 16-byte-aligned (HUM Ch 18.3.1 p 796).

Definition at line 196 of file main.c.

Referenced by dtc_arm_bringup_or_halt(), dtc_arm_program_ti(), dtc_coh_program_ti(), dtc_coh_run_once(), dtc_demo_bringup_or_halt(), and dtc_demo_program_ti().

◆ s_dtc_vt

uint32_t s_dtc_vt[k_dtc_arm_vt_entries]

static

DTC vector table – one 4-byte TI start address per IELSR slot.

Warning: 1 KB-aligned: DTCVBR requires the lower 10 bits be 0.

Definition at line 189 of file main.c.

Referenced by dtc_arm_bringup_or_halt(), dtc_coh_bringup_or_halt(), dtc_coh_program_ti(), and dtc_demo_bringup_or_halt().

◆ s_src

uint32_t s_src[k_dtc_arm_buf_words]

static

Source / destination buffers (32-bit aligned by element type).

Definition at line 181 of file main.c.

Referenced by cm_open_comic(), dtc_arm_all_match_src(), dtc_arm_fill(), dtc_arm_program_ti(), dtc_arm_run_armed(), dtc_coh_fill_buffers(), dtc_coh_program_ti(), dtc_coh_run_once(), dtc_coh_verify(), dtc_demo_fill_buffers(), dtc_demo_program_ti(), dtc_demo_run_once(), dtc_demo_verify(), internal_fill_buffers(), internal_run_copy(), and internal_verify().

◆ s_tag

const char* s_tag = "dtc_arm"

static

Diagnostic / log tag.

Definition at line 70 of file main.c.

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ dtc_arm_byte_t

◆ dtc_arm_config_t

◆ dtc_arm_count_t

◆ dtc_arm_cra_t

◆ dtc_arm_event_t

◆ dtc_arm_mr_field_t

◆ dtc_arm_mr_pos_t

◆ dtc_arm_swevt_t

◆ dtc_arm_vt_geom_t

Function Documentation

◆ dtc_arm_all_equal()

◆ dtc_arm_all_match_src()

◆ dtc_arm_bringup_or_halt()

◆ dtc_arm_complete_cb()

◆ dtc_arm_fill()

◆ dtc_arm_panic_halt()

◆ dtc_arm_program_ti()

◆ dtc_arm_run_armed()

◆ dtc_arm_run_disarmed()

◆ dtc_arm_setup_or_halt()

◆ dtc_arm_swevt_isr()

◆ main()

Variable Documentation

◆ g_dtc_activations

◆ g_dtc_armed_ok

◆ g_dtc_disarmed_ok

◆ g_dtc_heartbeat

◆ g_dtc_isr_count

◆ k_dtc_arm_bad_msg

◆ k_dtc_arm_ok_msg

◆ s_dst

◆ s_dtc_slot

◆ s_dtc_ti

◆ s_dtc_vt

◆ s_src

◆ s_tag