main.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cache.h"
#include "ra8_cgc.h"
#include "ra8_dmac.h"
#include "ra8_dmac_regs.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_log.h"
#include "ra8_mstp.h"

typedef enum : uint32_t {
  k_dma_coh_baud       = 115200U,     
  k_dma_coh_buf_words  = 256U,        
  k_dma_coh_poll_limit = 100000U,     
  k_dma_coh_sentinel   = 0xA5A5A5A5U, 
} dma_coh_config_t;

typedef enum : uint8_t {
  k_dma_coh_channel = 0U,  
  k_dma_coh_byte_sh = 8U,  
  k_dma_coh_align   = 32U, 
} dma_coh_byte_t;

static const uint8_t s_dma_coh_pass_banner[] = "dma_coherency_hil: dma coherent PASS\r\n";

static const uint8_t s_dma_coh_fail_banner[] = "dma_coherency_hil: dma coherent FAIL\r\n";

alignas(k_dma_coh_align) static uint32_t s_src[k_dma_coh_buf_words];

alignas(k_dma_coh_align) static uint32_t s_dst[k_dma_coh_buf_words];

[[noreturn]] RA8_INTERNAL static void internal_park(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}

RA8_INTERNAL static void internal_setup_or_halt(void)
{
  if (ra8_cgc_init() != k_ra8_ok) {
    internal_park();
  }
  if (ra8_mstp_init() != k_ra8_ok) {
    internal_park();
  }
  if (ra8_board_uart_console_init((uint32_t)k_dma_coh_baud) != k_ra8_ok) {
    internal_park();
  }
  if (ra8_board_led_init(k_ra8_board_led1) != k_ra8_ok) {
    internal_park();
  }
  if (ra8_board_led_init(k_ra8_board_led2) != k_ra8_ok) {
    internal_park();
  }
}

RA8_INTERNAL static void internal_fill_buffers(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dma_coh_buf_words; ++i) {
    s_src[i] = i ^ (i >> (uint32_t)k_dma_coh_byte_sh);
    s_dst[i] = (uint32_t)k_dma_coh_sentinel;
  }
}

[[nodiscard]] RA8_INTERNAL static uint8_t internal_verify(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_dma_coh_buf_words; ++i) {
    if (s_dst[i] != s_src[i]) {
      return 0U;
    }
  }
  return 1U;
}

[[nodiscard]] RA8_INTERNAL static ra8_err_t internal_run_copy(void)
{
  /* clean-before: dirty src lines -> SRAM so the DMAC reads fresh bytes. */
  if (ra8_cache_dcache_clean_by_addr(s_src, (uint32_t)sizeof(s_src)) != k_ra8_ok) {
    return k_ra8_err_hw_error;
  }
 
  const ra8_dmac_config_t cfg = {
    .src         = (uint32_t)(uintptr_t)s_src,
    .dst         = (uint32_t)(uintptr_t)s_dst,
    .count       = (uint16_t)k_dma_coh_buf_words,
    .block_count = 1U,
    .width       = k_ra8_dmac_width_word,
    .src_inc     = true,
    .dst_inc     = true,
  };
  ra8_err_t err = ra8_dmac_start_block((uint8_t)k_dma_coh_channel, &cfg);
  if (err != k_ra8_ok) {
    return err;
  }
 
  volatile r_dmac_channel_regs_t* reg = ra8_dmac((uint8_t)k_dma_coh_channel);
  if (reg == nullptr) {
    (void)ra8_dmac_stop((uint8_t)k_dma_coh_channel);
    return k_ra8_err_hw_error;
  }
 
  /* Software trigger: assert DMREQ.SWREQ to request the block transfer.
   * HUM Ch 17.2.15 p 744: write SWREQ=1; the bit auto-clears when the
   * controller accepts the request (CLRS=0 is the reset default). */
  reg->DMREQ = (uint8_t)k_ra8_dmreq_swreq_mask;
 
  /* Poll DMSTS.ACT until the controller goes idle.
   * HUM Ch 17.2.16 p 745: ACT clears when the transfer completes. */
  bool done = false;
  for (uint32_t i = 0U; i < (uint32_t)k_dma_coh_poll_limit; ++i) {
    if ((reg->DMSTS & (uint8_t)k_ra8_dmsts_act_mask) == 0U) {
      done = true;
      break;
    }
  }
  err = ra8_dmac_stop((uint8_t)k_dma_coh_channel);
  if (!done) {
    return k_ra8_err_hw_timeout;
  }
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* invalidate-after: drop stale dst lines so the verify reads SRAM. */
  if (ra8_cache_dcache_invalidate_by_addr(s_dst, (uint32_t)sizeof(s_dst)) != k_ra8_ok) {
    return k_ra8_err_hw_error;
  }
  return k_ra8_ok;
}

RA8_INTERNAL static void internal_report(uint8_t ok)
{
  if (ok != 0U) {
    (void)ra8_board_uart_console_write(s_dma_coh_pass_banner,
                                       (size_t)(sizeof(s_dma_coh_pass_banner) - 1U));
    (void)ra8_board_uart_console_flush();
    ra8_log_info("dma_coherency_hil", "dma coherent PASS");
    (void)ra8_board_led_toggle(k_ra8_board_led1);
  } else {
    (void)ra8_board_uart_console_write(s_dma_coh_fail_banner,
                                       (size_t)(sizeof(s_dma_coh_fail_banner) - 1U));
    (void)ra8_board_uart_console_flush();
    ra8_log_info("dma_coherency_hil", "dma coherent FAIL");
    (void)ra8_board_led_toggle(k_ra8_board_led2);
  }
}

void main(void)
{
  internal_setup_or_halt();
  ra8_isr_globals_enable();
 
  internal_fill_buffers();
  const ra8_err_t err = internal_run_copy();
  const uint8_t   ok  = (err == k_ra8_ok && internal_verify() != 0U) ? 1U : 0U;
  internal_report(ok);
 
  internal_park();
}