r_dmac_channel_regs_t Struct Reference

Per-channel DMAC register window. More...

#include <ra8_dmac_regs.h>

Data Fields
volatile uint32_t	DMSAR
	+0x00 Source address.
volatile uint32_t	DMDAR
	+0x04 Destination address.
volatile uint32_t	DMCRA
	+0x08 Transfer count (DMCRAL/DMCRAH).
volatile uint32_t	DMCRB
	+0x0C Block transfer count.
volatile uint16_t	DMTMD
	+0x10 Transfer Mode.
volatile uint8_t	_r0
	+0x12 reserved.
volatile uint8_t	DMINT
	+0x13 Interrupt Setting.
volatile uint16_t	DMAMD
	+0x14 Address Mode.
volatile uint16_t	_r1
	+0x16 reserved.
volatile uint32_t	DMOFR
	+0x18 Offset Register.
volatile uint8_t	DMCNT
	+0x1C Transfer Enable (bit DTE).
volatile uint8_t	DMREQ
	+0x1D Software Start (SWREQ/CLRS).
volatile uint8_t	DMSTS
	+0x1E Status (ESIF/DTIF/ACT).
volatile uint8_t	_r2
	+0x1F reserved.
volatile uint32_t	DMSRR
	+0x20 Source Reload Address.
volatile uint32_t	DMDRR
	+0x24 Dest Reload Address.
volatile uint32_t	DMSBS
	+0x28 Source Buffer Size.
volatile uint32_t	DMDBS
	+0x2C Dest Buffer Size.
volatile uint8_t	DMBWR
	+0x30 Bufferable Write Enable.
volatile uint8_t	_r3
	+0x31 reserved.
volatile uint16_t	_r4
	+0x32 reserved.
volatile uint8_t	_r5 [k_ra8_dmac_tail_padding]
	Reserved.

Detailed Description

Per-channel DMAC register window.

Layout verified against FSP R_DMAC0_Type in R7KA8D2KF_core0.h lines 5681-5871. Size = 52 (0x34) bytes per channel, with 12 bytes of tail padding up to the 0x40 channel stride.

Definition at line 69 of file ra8_dmac_regs.h.

Field Documentation

_r0

volatile uint8_t r_dmac_channel_regs_t::_r0

+0x12 reserved.

Definition at line 75 of file ra8_dmac_regs.h.

_r1

volatile uint16_t r_dmac_channel_regs_t::_r1

+0x16 reserved.

Definition at line 78 of file ra8_dmac_regs.h.

_r2

volatile uint8_t r_dmac_channel_regs_t::_r2

+0x1F reserved.

Definition at line 83 of file ra8_dmac_regs.h.

_r3

volatile uint8_t r_dmac_channel_regs_t::_r3

+0x31 reserved.

Definition at line 89 of file ra8_dmac_regs.h.

_r4

volatile uint16_t r_dmac_channel_regs_t::_r4

+0x32 reserved.

Definition at line 90 of file ra8_dmac_regs.h.

_r5

volatile uint8_t r_dmac_channel_regs_t::_r5[k_ra8_dmac_tail_padding]

Reserved.

Definition at line 91 of file ra8_dmac_regs.h.

DMAMD

volatile uint16_t r_dmac_channel_regs_t::DMAMD

+0x14 Address Mode.

Definition at line 77 of file ra8_dmac_regs.h.

Referenced by internal_program_channel(), and ra8_dmac_set_address_mode().

DMBWR

volatile uint8_t r_dmac_channel_regs_t::DMBWR

+0x30 Bufferable Write Enable.

Definition at line 88 of file ra8_dmac_regs.h.

DMCNT

volatile uint8_t r_dmac_channel_regs_t::DMCNT

+0x1C Transfer Enable (bit DTE).

Definition at line 80 of file ra8_dmac_regs.h.

Referenced by internal_program_channel(), ra8_dmac_start(), and ra8_dmac_stop().

DMCRA

volatile uint32_t r_dmac_channel_regs_t::DMCRA

+0x08 Transfer count (DMCRAL/DMCRAH).

Definition at line 72 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

DMCRB

volatile uint32_t r_dmac_channel_regs_t::DMCRB

+0x0C Block transfer count.

Definition at line 73 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

DMDAR

volatile uint32_t r_dmac_channel_regs_t::DMDAR

+0x04 Destination address.

Definition at line 71 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

DMDBS

volatile uint32_t r_dmac_channel_regs_t::DMDBS

+0x2C Dest Buffer Size.

Definition at line 87 of file ra8_dmac_regs.h.

DMDRR

volatile uint32_t r_dmac_channel_regs_t::DMDRR

+0x24 Dest Reload Address.

Definition at line 85 of file ra8_dmac_regs.h.

DMINT

volatile uint8_t r_dmac_channel_regs_t::DMINT

+0x13 Interrupt Setting.

Definition at line 76 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

DMOFR

volatile uint32_t r_dmac_channel_regs_t::DMOFR

+0x18 Offset Register.

Definition at line 79 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

DMREQ

volatile uint8_t r_dmac_channel_regs_t::DMREQ

+0x1D Software Start (SWREQ/CLRS).

Definition at line 81 of file ra8_dmac_regs.h.

Referenced by internal_run_copy(), and ra8_dmac_software_trigger().

DMSAR

volatile uint32_t r_dmac_channel_regs_t::DMSAR

+0x00 Source address.

Definition at line 70 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

DMSBS

volatile uint32_t r_dmac_channel_regs_t::DMSBS

+0x28 Source Buffer Size.

Definition at line 86 of file ra8_dmac_regs.h.

DMSRR

volatile uint32_t r_dmac_channel_regs_t::DMSRR

+0x20 Source Reload Address.

Definition at line 84 of file ra8_dmac_regs.h.

DMSTS

volatile uint8_t r_dmac_channel_regs_t::DMSTS

+0x1E Status (ESIF/DTIF/ACT).

Definition at line 82 of file ra8_dmac_regs.h.

Referenced by internal_run_copy(), ra8_dmac_is_active(), and ra8_dmac_wait_idle().

DMTMD

volatile uint16_t r_dmac_channel_regs_t::DMTMD

+0x10 Transfer Mode.

Definition at line 74 of file ra8_dmac_regs.h.

Referenced by internal_program_channel().

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The documentation for this struct was generated from the following file:

• libs/ra8_hal/inc/ra8_dmac_regs.h