ra8_dmac_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
 
/* =============================================================================
 * Base addresses (DMAC0 + shared module-control bank)
 * =============================================================================
 */
 
typedef enum : uintptr_t {
  k_ra8_dmac0_base_addr = 0x4000A000UL, 
  k_ra8_dma_base_addr   = 0x4000A800UL, 
} ra8_dmac_addr_t;
 
typedef enum : uint8_t {
  k_ra8_dmac_channel_count  = 8U,    
  k_ra8_dmac_channel_stride = 0x40U, 
  k_ra8_dmac_tail_padding   = 0x0CU, 
} ra8_dmac_limits_t;
 
/* =============================================================================
 * Per-channel register window
 * =============================================================================
 */

typedef struct {
  volatile uint32_t DMSAR;                        
  volatile uint32_t DMDAR;                        
  volatile uint32_t DMCRA;                        
  volatile uint32_t DMCRB;                        
  volatile uint16_t DMTMD;                        
  volatile uint8_t  _r0;                          
  volatile uint8_t  DMINT;                        
  volatile uint16_t DMAMD;                        
  volatile uint16_t _r1;                          
  volatile uint32_t DMOFR;                        
  volatile uint8_t  DMCNT;                        
  volatile uint8_t  DMREQ;                        
  volatile uint8_t  DMSTS;                        
  volatile uint8_t  _r2;                          
  volatile uint32_t DMSRR;                        
  volatile uint32_t DMDRR;                        
  volatile uint32_t DMSBS;                        
  volatile uint32_t DMDBS;                        
  volatile uint8_t  DMBWR;                        
  volatile uint8_t  _r3;                          
  volatile uint16_t _r4;                          
  volatile uint8_t  _r5[k_ra8_dmac_tail_padding]; 
} r_dmac_channel_regs_t;
 
/* =============================================================================
 * Shared DMA module-control bank (R_DMA at 0x4000A800)
 * =============================================================================
 */
 
typedef enum : uint8_t {
  k_ra8_dma_delsr_count = 8U,  
  k_ra8_dma_pad0_words  = 3U,  
  k_ra8_dma_pad1_words  = 11U, 
  k_ra8_dma_pad2_words  = 15U, 
} ra8_dma_shared_limits_t;

typedef struct {
  volatile uint8_t  DMAST;                        
  volatile uint8_t  _r0;                          
  volatile uint16_t _r1;                          
  volatile uint32_t _r2[k_ra8_dma_pad0_words];    
  volatile uint8_t  DMCTL;                        
  volatile uint8_t  _r3;                          
  volatile uint16_t _r4;                          
  volatile uint32_t _r5[k_ra8_dma_pad1_words];    
  volatile uint32_t DMECHR;                       
  volatile uint32_t _r6[k_ra8_dma_pad2_words];    
  volatile uint32_t DELSR[k_ra8_dma_delsr_count]; 
} r_dma_shared_regs_t;
 
/* =============================================================================
 * DMTMD bit positions / masks (HUM 17.2.10, p 738)
 * =============================================================================
 */
 
typedef enum : uint16_t {
  k_ra8_dmtmd_dctg_pos = 0U,  
  k_ra8_dmtmd_sz_pos   = 8U,  
  k_ra8_dmtmd_tkp_pos  = 10U, 
  k_ra8_dmtmd_dts_pos  = 12U, 
  k_ra8_dmtmd_md_pos   = 14U, 
} ra8_dmtmd_pos_t;
 
typedef enum : uint16_t {
  k_ra8_dmtmd_dctg_mask = (uint16_t)(0x3U << k_ra8_dmtmd_dctg_pos), 
  k_ra8_dmtmd_sz_mask   = (uint16_t)(0x3U << k_ra8_dmtmd_sz_pos),   
  k_ra8_dmtmd_tkp_mask  = (uint16_t)(0x1U << k_ra8_dmtmd_tkp_pos),  
  k_ra8_dmtmd_dts_mask  = (uint16_t)(0x3U << k_ra8_dmtmd_dts_pos),  
  k_ra8_dmtmd_md_mask   = (uint16_t)(0x3U << k_ra8_dmtmd_md_pos),   
} ra8_dmtmd_mask_t;
 
typedef enum : uint16_t {
  k_ra8_dmtmd_dctg_software = 0x0U, 
  k_ra8_dmtmd_dctg_hardware = 0x1U, 
} ra8_dmtmd_dctg_t;
 
typedef enum : uint16_t {
  k_ra8_dmtmd_sz_byte = 0x0U, 
  k_ra8_dmtmd_sz_half = 0x1U, 
  k_ra8_dmtmd_sz_word = 0x2U, 
  k_ra8_dmtmd_sz_long = 0x3U, 
} ra8_dmtmd_sz_t;
 
typedef enum : uint16_t {
  k_ra8_dmtmd_dts_dest_repeat = 0x0U, 
  k_ra8_dmtmd_dts_src_repeat  = 0x1U, 
  k_ra8_dmtmd_dts_none        = 0x2U, 
} ra8_dmtmd_dts_t;
 
typedef enum : uint16_t {
  k_ra8_dmtmd_md_normal       = 0x0U, 
  k_ra8_dmtmd_md_repeat       = 0x1U, 
  k_ra8_dmtmd_md_block        = 0x2U, 
  k_ra8_dmtmd_md_repeat_block = 0x3U, 
} ra8_dmtmd_md_t;
 
/* =============================================================================
 * DMINT bit positions (HUM 17.2.11, p 739)
 * =============================================================================
 */
 
typedef enum : uint8_t {
  k_ra8_dmint_darie_pos = 0U, 
  k_ra8_dmint_sarie_pos = 1U, 
  k_ra8_dmint_rptie_pos = 2U, 
  k_ra8_dmint_esie_pos  = 3U, 
  k_ra8_dmint_dtie_pos  = 4U, 
} ra8_dmint_pos_t;
 
typedef enum : uint8_t {
  k_ra8_dmint_darie_mask = (uint8_t)(0x1U << k_ra8_dmint_darie_pos), 
  k_ra8_dmint_sarie_mask = (uint8_t)(0x1U << k_ra8_dmint_sarie_pos), 
  k_ra8_dmint_rptie_mask = (uint8_t)(0x1U << k_ra8_dmint_rptie_pos), 
  k_ra8_dmint_esie_mask  = (uint8_t)(0x1U << k_ra8_dmint_esie_pos),  
  k_ra8_dmint_dtie_mask  = (uint8_t)(0x1U << k_ra8_dmint_dtie_pos),  
} ra8_dmint_mask_t;
 
/* =============================================================================
 * DMAMD bit positions (HUM 17.2.12, p 741)
 * =============================================================================
 */
 
typedef enum : uint16_t {
  k_ra8_dmamd_dara_pos = 0U,  
  k_ra8_dmamd_dadr_pos = 5U,  
  k_ra8_dmamd_dm_pos   = 6U,  
  k_ra8_dmamd_sara_pos = 8U,  
  k_ra8_dmamd_sadr_pos = 13U, 
  k_ra8_dmamd_sm_pos   = 14U, 
} ra8_dmamd_pos_t;
 
typedef enum : uint16_t {
  k_ra8_dmamd_dara_mask = (uint16_t)(0x1FU << k_ra8_dmamd_dara_pos), 
  k_ra8_dmamd_dadr_mask = (uint16_t)(0x1U << k_ra8_dmamd_dadr_pos),  
  k_ra8_dmamd_dm_mask   = (uint16_t)(0x3U << k_ra8_dmamd_dm_pos),    
  k_ra8_dmamd_sara_mask = (uint16_t)(0x1FU << k_ra8_dmamd_sara_pos), 
  k_ra8_dmamd_sadr_mask = (uint16_t)(0x1U << k_ra8_dmamd_sadr_pos),  
  k_ra8_dmamd_sm_mask   = (uint16_t)(0x3U << k_ra8_dmamd_sm_pos),    
} ra8_dmamd_mask_t;
 
typedef enum : uint16_t {
  k_ra8_dmamd_addr_fixed     = 0x0U, 
  k_ra8_dmamd_addr_offset    = 0x1U, 
  k_ra8_dmamd_addr_increment = 0x2U, 
  k_ra8_dmamd_addr_decrement = 0x3U, 
} ra8_dmamd_addr_mode_t;
 
/* =============================================================================
 * DMCNT, DMREQ, DMSTS, DMAST bit positions
 * =============================================================================
 */
 
typedef enum : uint8_t {
  k_ra8_dmcnt_dte_pos  = 0U,   
  k_ra8_dmcnt_dte_mask = 0x1U, 
} ra8_dmcnt_bits_t;
 
typedef enum : uint8_t {
  k_ra8_dmreq_swreq_pos  = 0U,                                       
  k_ra8_dmreq_clrs_pos   = 4U,                                       
  k_ra8_dmreq_swreq_mask = (uint8_t)(0x1U << k_ra8_dmreq_swreq_pos), 
  k_ra8_dmreq_clrs_mask  = (uint8_t)(0x1U << k_ra8_dmreq_clrs_pos),  
} ra8_dmreq_bits_t;
 
typedef enum : uint8_t {
  k_ra8_dmsts_esif_pos  = 0U,                                      
  k_ra8_dmsts_dtif_pos  = 4U,                                      
  k_ra8_dmsts_act_pos   = 7U,                                      
  k_ra8_dmsts_esif_mask = (uint8_t)(0x1U << k_ra8_dmsts_esif_pos), 
  k_ra8_dmsts_dtif_mask = (uint8_t)(0x1U << k_ra8_dmsts_dtif_pos), 
  k_ra8_dmsts_act_mask  = (uint8_t)(0x1U << k_ra8_dmsts_act_pos),  
} ra8_dmsts_bits_t;
 
typedef enum : uint8_t {
  k_ra8_dmast_dmst_pos  = 0U,   
  k_ra8_dmast_dmst_mask = 0x1U, 
} ra8_dmast_bits_t;
 
/* =============================================================================
 * DMCRA halves (HUM 17.2.8) and DMSBS/DMDBS halves (HUM 17.2.17/18)
 * =============================================================================
 */
 
typedef enum : uint32_t {
  k_ra8_dmcra_low_pos   = 0U,                             
  k_ra8_dmcra_low_mask  = 0x3FFU << k_ra8_dmcra_low_pos,  
  k_ra8_dmcra_high_pos  = 16U,                            
  k_ra8_dmcra_high_mask = 0x3FFU << k_ra8_dmcra_high_pos, 
} ra8_dmcra_bits_t;
 
typedef enum : uint32_t {
  k_ra8_dmbs_low_pos   = 0U,                                       
  k_ra8_dmbs_low_mask  = 0xFFFFU << k_ra8_dmbs_low_pos,            
  k_ra8_dmbs_high_pos  = 16U,                                      
  k_ra8_dmbs_high_mask = (uint32_t)0xFFFFU << k_ra8_dmbs_high_pos, 
} ra8_dmbs_bits_t;
 
/* =============================================================================
 * Accessors
 * =============================================================================
 */

RA8_HW_REGISTER_ACCESS
static inline volatile r_dmac_channel_regs_t* ra8_dmac(uint8_t channel)
{
  if (channel >= k_ra8_dmac_channel_count) {
    return nullptr;
  }
  return (
    volatile r_dmac_channel_regs_t*)(k_ra8_dmac0_base_addr +
                                     ((uintptr_t)channel * (uintptr_t)k_ra8_dmac_channel_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile r_dma_shared_regs_t* ra8_dma_shared(void)
{
  return (volatile r_dma_shared_regs_t*)k_ra8_dma_base_addr;
}
 
#ifdef __cplusplus
}
#endif