DMAC (Direct Memory Access Controller) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_dmac_regs.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	r_dmac_channel_regs_t
	Per-channel DMAC register window. More...
struct	r_dma_shared_regs_t
	Shared DMA module-control register window. More...

Enumerations
enum	ra8_dmac_addr_t : uintptr_t { k_ra8_dmac0_base_addr = 0x4000A000UL , k_ra8_dma_base_addr = 0x4000A800UL }
enum	ra8_dmac_limits_t : uint8_t { k_ra8_dmac_channel_count = 8U , k_ra8_dmac_channel_stride = 0x40U , k_ra8_dmac_tail_padding = 0x0CU }
enum	ra8_dma_shared_limits_t : uint8_t { k_ra8_dma_delsr_count = 8U , k_ra8_dma_pad0_words = 3U , k_ra8_dma_pad1_words = 11U , k_ra8_dma_pad2_words = 15U }
enum	ra8_dmtmd_pos_t : uint16_t { k_ra8_dmtmd_dctg_pos = 0U , k_ra8_dmtmd_sz_pos = 8U , k_ra8_dmtmd_tkp_pos = 10U , k_ra8_dmtmd_dts_pos = 12U , k_ra8_dmtmd_md_pos = 14U }
enum	ra8_dmtmd_mask_t : uint16_t { k_ra8_dmtmd_dctg_mask = (uint16_t)(0x3U << k_ra8_dmtmd_dctg_pos) , k_ra8_dmtmd_sz_mask = (uint16_t)(0x3U << k_ra8_dmtmd_sz_pos) , k_ra8_dmtmd_tkp_mask = (uint16_t)(0x1U << k_ra8_dmtmd_tkp_pos) , k_ra8_dmtmd_dts_mask = (uint16_t)(0x3U << k_ra8_dmtmd_dts_pos) , k_ra8_dmtmd_md_mask = (uint16_t)(0x3U << k_ra8_dmtmd_md_pos) }
enum	ra8_dmtmd_dctg_t : uint16_t { k_ra8_dmtmd_dctg_software = 0x0U , k_ra8_dmtmd_dctg_hardware = 0x1U }
enum	ra8_dmtmd_sz_t : uint16_t { k_ra8_dmtmd_sz_byte = 0x0U , k_ra8_dmtmd_sz_half = 0x1U , k_ra8_dmtmd_sz_word = 0x2U , k_ra8_dmtmd_sz_long = 0x3U }
enum	ra8_dmtmd_dts_t : uint16_t { k_ra8_dmtmd_dts_dest_repeat = 0x0U , k_ra8_dmtmd_dts_src_repeat = 0x1U , k_ra8_dmtmd_dts_none = 0x2U }
enum	ra8_dmtmd_md_t : uint16_t { k_ra8_dmtmd_md_normal = 0x0U , k_ra8_dmtmd_md_repeat = 0x1U , k_ra8_dmtmd_md_block = 0x2U , k_ra8_dmtmd_md_repeat_block = 0x3U }
enum	ra8_dmint_pos_t : uint8_t { k_ra8_dmint_darie_pos = 0U , k_ra8_dmint_sarie_pos = 1U , k_ra8_dmint_rptie_pos = 2U , k_ra8_dmint_esie_pos = 3U , k_ra8_dmint_dtie_pos = 4U }
enum	ra8_dmint_mask_t : uint8_t { k_ra8_dmint_darie_mask = (uint8_t)(0x1U << k_ra8_dmint_darie_pos) , k_ra8_dmint_sarie_mask = (uint8_t)(0x1U << k_ra8_dmint_sarie_pos) , k_ra8_dmint_rptie_mask = (uint8_t)(0x1U << k_ra8_dmint_rptie_pos) , k_ra8_dmint_esie_mask = (uint8_t)(0x1U << k_ra8_dmint_esie_pos) , k_ra8_dmint_dtie_mask = (uint8_t)(0x1U << k_ra8_dmint_dtie_pos) }
enum	ra8_dmamd_pos_t : uint16_t { k_ra8_dmamd_dara_pos = 0U , k_ra8_dmamd_dadr_pos = 5U , k_ra8_dmamd_dm_pos = 6U , k_ra8_dmamd_sara_pos = 8U , k_ra8_dmamd_sadr_pos = 13U , k_ra8_dmamd_sm_pos = 14U }
enum	ra8_dmamd_mask_t : uint16_t { k_ra8_dmamd_dara_mask = (uint16_t)(0x1FU << k_ra8_dmamd_dara_pos) , k_ra8_dmamd_dadr_mask = (uint16_t)(0x1U << k_ra8_dmamd_dadr_pos) , k_ra8_dmamd_dm_mask = (uint16_t)(0x3U << k_ra8_dmamd_dm_pos) , k_ra8_dmamd_sara_mask = (uint16_t)(0x1FU << k_ra8_dmamd_sara_pos) , k_ra8_dmamd_sadr_mask = (uint16_t)(0x1U << k_ra8_dmamd_sadr_pos) , k_ra8_dmamd_sm_mask = (uint16_t)(0x3U << k_ra8_dmamd_sm_pos) }
enum	ra8_dmamd_addr_mode_t : uint16_t { k_ra8_dmamd_addr_fixed = 0x0U , k_ra8_dmamd_addr_offset = 0x1U , k_ra8_dmamd_addr_increment = 0x2U , k_ra8_dmamd_addr_decrement = 0x3U }
enum	ra8_dmcnt_bits_t : uint8_t { k_ra8_dmcnt_dte_pos = 0U , k_ra8_dmcnt_dte_mask = 0x1U }
enum	ra8_dmreq_bits_t : uint8_t { k_ra8_dmreq_swreq_pos = 0U , k_ra8_dmreq_clrs_pos = 4U , k_ra8_dmreq_swreq_mask = (uint8_t)(0x1U << k_ra8_dmreq_swreq_pos) , k_ra8_dmreq_clrs_mask = (uint8_t)(0x1U << k_ra8_dmreq_clrs_pos) }
enum	ra8_dmsts_bits_t : uint8_t { k_ra8_dmsts_esif_pos = 0U , k_ra8_dmsts_dtif_pos = 4U , k_ra8_dmsts_act_pos = 7U , k_ra8_dmsts_esif_mask = (uint8_t)(0x1U << k_ra8_dmsts_esif_pos) , k_ra8_dmsts_dtif_mask = (uint8_t)(0x1U << k_ra8_dmsts_dtif_pos) , k_ra8_dmsts_act_mask = (uint8_t)(0x1U << k_ra8_dmsts_act_pos) }
enum	ra8_dmast_bits_t : uint8_t { k_ra8_dmast_dmst_pos = 0U , k_ra8_dmast_dmst_mask = 0x1U }
enum	ra8_dmcra_bits_t : uint32_t { k_ra8_dmcra_low_pos = 0U , k_ra8_dmcra_low_mask = 0x3FFU << k_ra8_dmcra_low_pos , k_ra8_dmcra_high_pos = 16U , k_ra8_dmcra_high_mask = 0x3FFU << k_ra8_dmcra_high_pos }
enum	ra8_dmbs_bits_t : uint32_t { k_ra8_dmbs_low_pos = 0U , k_ra8_dmbs_low_mask = 0xFFFFU << k_ra8_dmbs_low_pos , k_ra8_dmbs_high_pos = 16U , k_ra8_dmbs_high_mask = (uint32_t)0xFFFFU << k_ra8_dmbs_high_pos }

Functions
static volatile r_dmac_channel_regs_t *	ra8_dmac (uint8_t channel)
	Pointer to DMAC channel channel (0..7), or NULL on error.
static volatile r_dma_shared_regs_t *	ra8_dma_shared (void)
	Pointer to the shared DMA module-control bank.

Detailed Description

DMAC (Direct Memory Access Controller) register layout for the RA8D2.

8-channel DMAC0 at 0x4000A000 with 0x40 bytes per channel. The shared DMA module-control bank lives at R_DMA_BASE = 0x4000A800 (DMAST, DMCTL, DMECHR, DELSR[0..7]). Each channel supports normal, repeat, block, and repeat-block transfer modes with flexible trigger sources routed through the ELC via DELSR.

Layout matches FSP R_DMAC0_Type (R7KA8D2KF_core0.h lines 5681-5871, size = 52 / 0x34 bytes per channel) and R_DMA_Type (lines 5610-5671, size = 160 / 0xa0 bytes for the shared bank).

Bit-field positions are derived from the HUM:

17.2.10 DMTMD: pp 738-739
17.2.11 DMINT: p 739
17.2.12 DMAMD: p 741
17.2.13 DMOFR: p 743
17.2.14 DMCNT: p 743
17.2.20 DMAST: p 749

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_dmac_regs.h.

Enumeration Type Documentation

◆ ra8_dma_shared_limits_t

enum ra8_dma_shared_limits_t : uint8_t

Enumerator
k_ra8_dma_delsr_count	One DELSR per channel.
k_ra8_dma_pad0_words	+0x04..0x0F: 12 bytes / 4 = 3 words.
k_ra8_dma_pad1_words	+0x14..0x3F: 44 bytes / 4 = 11 words.
k_ra8_dma_pad2_words	+0x44..0x7F: 60 bytes / 4 = 15 words.

Definition at line 99 of file ra8_dmac_regs.h.

◆ ra8_dmac_addr_t

enum ra8_dmac_addr_t : uintptr_t

Enumerator
k_ra8_dmac0_base_addr	DMAC0 channel 0 base.
k_ra8_dma_base_addr	Shared DMA module regs.

Definition at line 44 of file ra8_dmac_regs.h.

◆ ra8_dmac_limits_t

enum ra8_dmac_limits_t : uint8_t

Enumerator
k_ra8_dmac_channel_count	RA8 DMAC channel count.
k_ra8_dmac_channel_stride	RA8 DMAC channel stride.
k_ra8_dmac_tail_padding	Bytes after DMBWR up to stride.

Definition at line 49 of file ra8_dmac_regs.h.

◆ ra8_dmamd_addr_mode_t

enum ra8_dmamd_addr_mode_t : uint16_t

Enumerator
k_ra8_dmamd_addr_fixed	00b: address fixed.
k_ra8_dmamd_addr_offset	01b: offset addition.
k_ra8_dmamd_addr_increment	10b: increment.
k_ra8_dmamd_addr_decrement	11b: decrement.

Definition at line 220 of file ra8_dmac_regs.h.

◆ ra8_dmamd_mask_t

enum ra8_dmamd_mask_t : uint16_t

Enumerator
k_ra8_dmamd_dara_mask	RA8 dmamd dara mask.
k_ra8_dmamd_dadr_mask	RA8 dmamd dadr mask.
k_ra8_dmamd_dm_mask	RA8 dmamd dm mask.
k_ra8_dmamd_sara_mask	RA8 dmamd sara mask.
k_ra8_dmamd_sadr_mask	RA8 dmamd sadr mask.
k_ra8_dmamd_sm_mask	RA8 dmamd sm mask.

Definition at line 211 of file ra8_dmac_regs.h.

◆ ra8_dmamd_pos_t

enum ra8_dmamd_pos_t : uint16_t

Enumerator
k_ra8_dmamd_dara_pos	DARA[4:0] dst extended-repeat area.
k_ra8_dmamd_dadr_pos	DADR dst addr update select.
k_ra8_dmamd_dm_pos	DM[1:0] dst addr update mode.
k_ra8_dmamd_sara_pos	SARA[4:0] src extended-repeat area.
k_ra8_dmamd_sadr_pos	SADR src addr update select.
k_ra8_dmamd_sm_pos	SM[1:0] src addr update mode.

Definition at line 202 of file ra8_dmac_regs.h.

◆ ra8_dmast_bits_t

enum ra8_dmast_bits_t : uint8_t

Enumerator
k_ra8_dmast_dmst_pos	DMAST.DMST bit 0 (HUM 17.2.20, p 749).
k_ra8_dmast_dmst_mask	RA8 dmast dmst mask.

Definition at line 253 of file ra8_dmac_regs.h.

◆ ra8_dmbs_bits_t

enum ra8_dmbs_bits_t : uint32_t

Enumerator
k_ra8_dmbs_low_pos	RA8 dmbs low pos.
k_ra8_dmbs_low_mask	RA8 dmbs low mask.
k_ra8_dmbs_high_pos	RA8 dmbs high pos.
k_ra8_dmbs_high_mask	RA8 dmbs high mask.

Definition at line 270 of file ra8_dmac_regs.h.

◆ ra8_dmcnt_bits_t

enum ra8_dmcnt_bits_t : uint8_t

Enumerator
k_ra8_dmcnt_dte_pos	DMCNT.DTE bit 0 (HUM 17.2.14, p 743).
k_ra8_dmcnt_dte_mask	RA8 dmcnt dte mask.

Definition at line 232 of file ra8_dmac_regs.h.

◆ ra8_dmcra_bits_t

enum ra8_dmcra_bits_t : uint32_t

Enumerator
k_ra8_dmcra_low_pos	RA8 dmcra low pos.
k_ra8_dmcra_low_mask	RA8 dmcra low mask.
k_ra8_dmcra_high_pos	RA8 dmcra high pos.
k_ra8_dmcra_high_mask	RA8 dmcra high mask.

Definition at line 263 of file ra8_dmac_regs.h.

◆ ra8_dmint_mask_t

enum ra8_dmint_mask_t : uint8_t

Enumerator
k_ra8_dmint_darie_mask	RA8 dmint darie mask.
k_ra8_dmint_sarie_mask	RA8 dmint sarie mask.
k_ra8_dmint_rptie_mask	RA8 dmint rptie mask.
k_ra8_dmint_esie_mask	RA8 dmint esie mask.
k_ra8_dmint_dtie_mask	RA8 dmint dtie mask.

Definition at line 189 of file ra8_dmac_regs.h.

◆ ra8_dmint_pos_t

enum ra8_dmint_pos_t : uint8_t

Enumerator
k_ra8_dmint_darie_pos	DARIE: dst extended-repeat overflow IRQ.
k_ra8_dmint_sarie_pos	SARIE: src extended-repeat overflow IRQ.
k_ra8_dmint_rptie_pos	RPTIE: repeat-size end IRQ.
k_ra8_dmint_esie_pos	ESIE: transfer-escape end IRQ.
k_ra8_dmint_dtie_pos	DTIE: transfer-end IRQ.

Definition at line 181 of file ra8_dmac_regs.h.

◆ ra8_dmreq_bits_t

enum ra8_dmreq_bits_t : uint8_t

Enumerator
k_ra8_dmreq_swreq_pos	DMREQ.SWREQ bit 0.
k_ra8_dmreq_clrs_pos	DMREQ.CLRS bit 4.
k_ra8_dmreq_swreq_mask	RA8 dmreq swreq mask.
k_ra8_dmreq_clrs_mask	RA8 dmreq clrs mask.

Definition at line 237 of file ra8_dmac_regs.h.

◆ ra8_dmsts_bits_t

enum ra8_dmsts_bits_t : uint8_t

Enumerator
k_ra8_dmsts_esif_pos	DMSTS.ESIF bit 0.
k_ra8_dmsts_dtif_pos	DMSTS.DTIF bit 4.
k_ra8_dmsts_act_pos	DMSTS.ACT bit 7.
k_ra8_dmsts_esif_mask	RA8 dmsts esif mask.
k_ra8_dmsts_dtif_mask	RA8 dmsts dtif mask.
k_ra8_dmsts_act_mask	RA8 dmsts act mask.

Definition at line 244 of file ra8_dmac_regs.h.

◆ ra8_dmtmd_dctg_t

enum ra8_dmtmd_dctg_t : uint16_t

Enumerator
k_ra8_dmtmd_dctg_software	00b: software request.
k_ra8_dmtmd_dctg_hardware	01b: hardware request.

Definition at line 151 of file ra8_dmac_regs.h.

◆ ra8_dmtmd_dts_t

enum ra8_dmtmd_dts_t : uint16_t

Enumerator
k_ra8_dmtmd_dts_dest_repeat	00b: dest is repeat/block area.
k_ra8_dmtmd_dts_src_repeat	01b: src is repeat/block area.
k_ra8_dmtmd_dts_none	10b: no repeat/block area.

Definition at line 163 of file ra8_dmac_regs.h.

◆ ra8_dmtmd_mask_t

enum ra8_dmtmd_mask_t : uint16_t

Enumerator
k_ra8_dmtmd_dctg_mask	RA8 dmtmd dctg mask.
k_ra8_dmtmd_sz_mask	RA8 dmtmd sz mask.
k_ra8_dmtmd_tkp_mask	RA8 dmtmd tkp mask.
k_ra8_dmtmd_dts_mask	RA8 dmtmd dts mask.
k_ra8_dmtmd_md_mask	RA8 dmtmd md mask.

Definition at line 143 of file ra8_dmac_regs.h.

◆ ra8_dmtmd_md_t

enum ra8_dmtmd_md_t : uint16_t

Enumerator
k_ra8_dmtmd_md_normal	00b: normal transfer.
k_ra8_dmtmd_md_repeat	01b: repeat transfer.
k_ra8_dmtmd_md_block	10b: block transfer.
k_ra8_dmtmd_md_repeat_block	11b: repeat-block transfer.

Definition at line 169 of file ra8_dmac_regs.h.

◆ ra8_dmtmd_pos_t

enum ra8_dmtmd_pos_t : uint16_t

Enumerator
k_ra8_dmtmd_dctg_pos	DCTG[1:0] bit 0..1 – request source.
k_ra8_dmtmd_sz_pos	SZ[1:0] bit 8..9 – transfer size.
k_ra8_dmtmd_tkp_pos	TKP bit 10 – transfer keep.
k_ra8_dmtmd_dts_pos	DTS[1:0] bit 12..13 – repeat area.
k_ra8_dmtmd_md_pos	MD[1:0] bit 14..15 – mode.

Definition at line 135 of file ra8_dmac_regs.h.

◆ ra8_dmtmd_sz_t

enum ra8_dmtmd_sz_t : uint16_t

Enumerator
k_ra8_dmtmd_sz_byte	00b: 8-bit.
k_ra8_dmtmd_sz_half	01b: 16-bit.
k_ra8_dmtmd_sz_word	10b: 32-bit.
k_ra8_dmtmd_sz_long	11b: 64-bit.

Definition at line 156 of file ra8_dmac_regs.h.

Function Documentation

◆ ra8_dma_shared()

volatile r_dma_shared_regs_t * ra8_dma_shared ( void )

inlinestatic

Pointer to the shared DMA module-control bank.

Definition at line 296 of file ra8_dmac_regs.h.

References k_ra8_dma_base_addr.

Referenced by ra8_dmac_start().

◆ ra8_dmac()

volatile r_dmac_channel_regs_t * ra8_dmac ( uint8_t channel )