Event Link Controller (ELC) register layout for the Renesas RA8D2. More...

#include <stdint.h>

Include dependency graph for ra8_elc_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_elc_addr_t : uintptr_t { k_ra8_elc_base_addr = 0x40201000UL }
enum	ra8_elc_off_t : uint16_t { k_ra8_elc_off_elcr = 0x000U , k_ra8_elc_off_elsegr0 = 0x004U , k_ra8_elc_off_elsegr1 = 0x008U , k_ra8_elc_off_elsegr2 = 0x00CU , k_ra8_elc_off_elsegr3 = 0x010U , k_ra8_elc_off_elsr0 = 0x020U , k_ra8_elc_off_elcsara = 0x100U , k_ra8_elc_off_elcsarb = 0x104U , k_ra8_elc_off_elcsarc = 0x108U , k_ra8_elc_elsr_stride = 0x004U , k_ra8_elc_elsegr_stride = 0x004U }
	Byte offsets within the ELC register block at k_ra8_elc_base_addr. More...
enum	ra8_elc_elsegr_step_t : uint8_t { k_ra8_elc_elsegr_step_unlock = 0x00U , k_ra8_elc_elsegr_step_arm = 0x40U , k_ra8_elc_elsegr_step_trigger = 0x41U }
	3-step write-protect unlock sequence required by ELSEGRn. More...
enum	ra8_elc_elcr_bit_t : uint8_t { k_ra8_elcr_bit_elcon = 7U }
	Bit positions inside the ELCR register. More...
enum	ra8_elc_event_t : uint16_t { k_ra8_elc_event_none = 0x000U , k_ra8_elc_event_icu_irq0 = 0x001U , k_ra8_elc_event_icu_irq1 = 0x002U , k_ra8_elc_event_icu_irq12 = 0x00DU , k_ra8_elc_event_icu_irq13 = 0x00EU , k_ra8_elc_event_icu_irq15 = 0x010U , k_ra8_elc_event_npu_irq = 0x067U , k_ra8_elc_event_ulpt0_ulpti = 0x080U , k_ra8_elc_event_ulpt0_ulptcmai = 0x081U , k_ra8_elc_event_ulpt0_ulptcmbi = 0x082U , k_ra8_elc_event_can0_mram_eri = 0x338U , k_ra8_elc_event_can1_mram_eri = 0x339U , k_ra8_elc_event_usbfs_int = 0x09AU , k_ra8_elc_event_usbfs_resume = 0x09BU , k_ra8_elc_event_pdm_dat0 = 0x0BFU , k_ra8_elc_event_pdm_dat1 = 0x0C0U , k_ra8_elc_event_pdm_dat2 = 0x0C1U , k_ra8_elc_event_usbhs_int_resume = 0x2C3U }
	Partial list of ELC events (populate as drivers need them). More...

Detailed Description

Event Link Controller (ELC) register layout for the Renesas RA8D2.

The ELC lets one peripheral's event directly trigger another peripheral's input without CPU involvement. Register layout cross-verified against FSP R_ELC_Type in R7KA8D2KF_core0.h (size 0x11C, base 0x40201000).

Register map (at 0x40201000, HUM Ch 19, p 817..836):

Offset	Name	Width	Purpose
0x000	ELCR	8	Event Link Control Register (ELCON bit 7)
0x004	ELSEGR[0]	8	Software Event Gen 0 (3-byte stride padding)
0x008	ELSEGR[1]	8	Software Event Gen 1
0x00C	ELSEGR[2]	8	Software Event Gen 2
0x010	ELSEGR[3]	8	Software Event Gen 3
0x020	ELSR[n]	16	Event Link Setting Register n (n = 0..52)
0x100	ELCSARA	32	Security attribution (ELCR + ELSEGR0..3 bits)
0x104	ELCSARB	32	Security attribution for ELSR0..31
0x108	ELCSARC	32	Security attribution for ELSR32..52
0x110	ELCPARA	32	Privilege attribution (ELCR + ELSEGR0..3)
0x114	ELCPARB	32	Privilege attribution for ELSR0..31
0x118	ELCPARC	32	Privilege attribution for ELSR32..52

The ELS field inside ELSR.HA is 10 bits (mask 0x3FF), so a uint16_t fits any valid event number.

Note: This header exposes the base + offsets only. The full device-specific event enum lives in fsp/ra/fsp/src/bsp/mcu/ra8d2/bsp_elc.h. Copy in the entries the firmware actually wires up rather than the whole list.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_elc_regs.h.

Enumeration Type Documentation

◆ ra8_elc_addr_t

enum ra8_elc_addr_t : uintptr_t

Enumerator
k_ra8_elc_base_addr	RA8 elc base address.

Definition at line 50 of file ra8_elc_regs.h.

◆ ra8_elc_elcr_bit_t

enum ra8_elc_elcr_bit_t : uint8_t

Bit positions inside the ELCR register.

HUM Ch 19.2.1 "ELCR : Event Link Control Register", p 817.

Enumerator
k_ra8_elcr_bit_elcon	ELCR.ELCON – global enable.

Definition at line 99 of file ra8_elc_regs.h.

◆ ra8_elc_elsegr_step_t

enum ra8_elc_elsegr_step_t : uint8_t

3-step write-protect unlock sequence required by ELSEGRn.

Per HUM Ch 19.2.2 "ELSEGRn : Event Link Software Event Generation Register n", p 817 (and FSP r_elc.c ELC_ELSEGRN_STEP1..3), a software event is generated by writing three values in sequence to clear WI, set WE, then set SEG. Any other value pattern is silently dropped by the hardware.

Enumerator
k_ra8_elc_elsegr_step_unlock	WI=0, WE=0, SEG=0 – clear write-disable.
k_ra8_elc_elsegr_step_arm	WI=0, WE=1, SEG=0 – arm SEG bit for write.
k_ra8_elc_elsegr_step_trigger	WI=0, WE=1, SEG=1 – fire software event.

Definition at line 87 of file ra8_elc_regs.h.

◆ ra8_elc_event_t

enum ra8_elc_event_t : uint16_t

Partial list of ELC events (populate as drivers need them).

Values taken from the RA8D2 Hardware User's Manual Ch 19 (HUM Table 19.2 "Event signal table") and verified against FSP bsp_elc.h for ra8d2. Only the entries the firmware actually wires up live here; see the manual (or fsp/ra/fsp/src/bsp/mcu/ra8d2/bsp_elc.h) for the full list.

Note: The ELS field inside ELSR.HA is 10 bits wide (R_ELC_ELSR_HA_ELS_Msk = 0x3FF), so legal event numbers are 0..1023; uint16_t is the smallest type that fits.

Enumerator
k_ra8_elc_event_none	Link disabled (HUM Ch 19.2.3 ELS=0).
k_ra8_elc_event_icu_irq0	External pin interrupt 0.
k_ra8_elc_event_icu_irq1	External pin interrupt 1.
k_ra8_elc_event_icu_irq12	External pin interrupt 12 (HUM Ch 14 ELC event 0x00D).
k_ra8_elc_event_icu_irq13	External pin interrupt 13 (HUM Ch 14 ELC event 0x00E).
k_ra8_elc_event_icu_irq15	External pin interrupt 15.
k_ra8_elc_event_npu_irq	Ethos-U55 NPU IRQ (RA8P1 only; RA8P1 HUM R01UH1064EJ Ch 19 Table 19.3). Absent on RA8D2; modelled here so the shared ISR registrar accepts the NPU event without a cast that no enumerator would match.
k_ra8_elc_event_ulpt0_ulpti	ULPT0 underflow (counter reaches 0). ULPT0_ULPTI per HUM Ch 19.2.3 Table 19.3 p 823. Used as the Software-Standby wake source.
k_ra8_elc_event_ulpt0_ulptcmai	ULPT0 compare-match A (ULPT0_ULPTCMAI, HUM Ch 19.2.3 Table 19.3 p 823).
k_ra8_elc_event_ulpt0_ulptcmbi	ULPT0 compare-match B (ULPT0_ULPTCMBI, HUM Ch 19.2.3 Table 19.3 p 823).
k_ra8_elc_event_can0_mram_eri	CANFD0 MRAM ECC error (HUM Ch 19 Table 19.3).
k_ra8_elc_event_can1_mram_eri	CANFD1 MRAM ECC error (HUM Ch 19 Table 19.3).
k_ra8_elc_event_usbfs_int	USBFS controller interrupt. Cross-checked against ra/fsp/src/bsp/mcu/ra8d2/bsp_elc.h line 133: ELC_EVENT_USBFS_INT = (0x09A) (HUM Ch 19 Table 19.3, Ch 36).
k_ra8_elc_event_usbfs_resume	USBFS resume from suspend. Cross-checked against ra/fsp/src/bsp/mcu/ra8d2/bsp_elc.h line 134: ELC_EVENT_USBFS_RESUME = (0x09B) (HUM Ch 19 Table 19.3, Ch 36).
k_ra8_elc_event_pdm_dat0	PDM channel 0 data reception.
k_ra8_elc_event_pdm_dat1	PDM channel 1 data reception.
k_ra8_elc_event_pdm_dat2	PDM channel 2 data reception.
k_ra8_elc_event_usbhs_int_resume	USBHS combined int + resume. Cross-checked against ra/fsp/src/bsp/mcu/ra8d2/bsp_elc.h line 347: ELC_EVENT_USBHS_USB_INT_RESUME = (0x2C3). RA8D2 collapses the separate USBR event from older RA parts into this single line (HUM Ch 19 Table 19.3, Ch 37).

Definition at line 118 of file ra8_elc_regs.h.

◆ ra8_elc_off_t

enum ra8_elc_off_t : uint16_t

Byte offsets within the ELC register block at k_ra8_elc_base_addr.

Cross-verified against FSP R_ELC_Type in R7KA8D2KF_core0.h (HUM Ch 19, p 817..836).

Enumerator
k_ra8_elc_off_elcr	ELCR: global enable bit ELCON @ bit 7 (8b).
k_ra8_elc_off_elsegr0	ELSEGR[0]: software event gen 0 (8b, stride 4).
k_ra8_elc_off_elsegr1	ELSEGR[1]: software event gen 1 (8b, stride 4).
k_ra8_elc_off_elsegr2	ELSEGR[2]: software event gen 2 (8b, stride 4).
k_ra8_elc_off_elsegr3	ELSEGR[3]: software event gen 3 (8b, stride 4).
k_ra8_elc_off_elsr0	ELSR[0]: first link slot, ELSR0..ELSR52 (16b, stride 4).
k_ra8_elc_off_elcsara	ELCSARA: security attribution (ELCR + ELSEGR).
k_ra8_elc_off_elcsarb	ELCSARB: security attribution for ELSR0..31.
k_ra8_elc_off_elcsarc	ELCSARC: security attribution for ELSR32..52.
k_ra8_elc_elsr_stride	Stride between ELSR slots.
k_ra8_elc_elsegr_stride	Stride between ELSEGR slots.

Definition at line 62 of file ra8_elc_regs.h.