DTC (Data Transfer Controller) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_dtc_regs.h:

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Data Structures
struct	r_dtc_regs_t
	DTC controller register block at 0x4000AC00. More...
struct	r_dtc_xfer_info_t
	One 16-byte Transfer Information (TI) block referenced by the DTC vector table. More...

Enumerations
enum	ra8_dtc_addr_t : uintptr_t { k_ra8_dtc_base_addr = 0x4000AC00UL }
enum	ra8_dtc_layout_t : uint8_t { k_ra8_dtc_xfer_info_size = 16U , k_ra8_dtc_vector_align = 16U }
enum	ra8_dtc_vector_align_t : uint16_t { k_ra8_dtc_vector_table_align = 1024U }
enum	ra8_dtc_dtccr_bits_t : uint8_t { k_ra8_dtccr_rrs_pos = 4U , k_ra8_dtccr_rrs_msk = 0x10U , k_ra8_dtccr_reserved3 = 0x08U , k_ra8_dtccr_rrs_disable = 0x08U , k_ra8_dtccr_rrs_enable = 0x18U }
enum	ra8_dtc_dtcst_bits_t : uint8_t { k_ra8_dtcst_dtcst_pos = 0U , k_ra8_dtcst_dtcst_msk = 0x1U }
enum	ra8_dtc_dtcsts_bits_t : uint16_t { k_ra8_dtcsts_vecn_msk = 0x00FFU , k_ra8_dtcsts_act_msk = 0x8000U }
enum	ra8_dtc_dtcadmod_bits_t : uint8_t { k_ra8_dtcadmod_short_msk = 0x1U }

Functions
static volatile r_dtc_regs_t *	ra8_dtc (void)
	Get pointer to the DTC controller register block.

Detailed Description

DTC (Data Transfer Controller) register layout for the RA8D2.

The DTC is a lighter-weight alternative to the DMAC for moving small amounts of data in response to peripheral interrupts. Its control registers live at 0x4000AC00. Transfer descriptors live in SRAM, reached through a two-level lookup: DTCVBR points at a vector table of 4-byte entries indexed by the activation-source vector number, and entry n (at DTCVBR + n*4) holds the start address of that source's 16-byte Transfer Information block (HUM Ch 18.3.1 "Allocating Transfer Information and DTC Vector Table" p 796, Figures 18.2/18.3 p 797-798).

Register-block layout verified against FSP R_DTC_Type in R7KA8D2KF_core0.h lines 6581-6732 (size = 48 / 0x30 bytes). Bit-field positions are derived from the HUM:

18.2.1 DTCCR : p 786
18.2.2 DTCVBR : p 787
18.2.3 DTCST : p 787
18.2.4 DTCSTS : p 788
18.2.5 DTCCR_SEC : p 788
18.2.6 DTCVBR_SEC: p 789
18.2.7 DTCDISP : p 789
18.2.8 DTEVR : p 790
18.2.9 DTCIBR : p 791
18.2.10 DTCOR : p 791
18.2.11 DTCSQE : p 792
18.2.12 DTCADMOD : p 793

Transfer Information layout (per HUM Figure 18.4 p 799) – each TI block is 16 bytes consisting of MRA, MRB, MRC, SAR, DAR, CRA, CRB. The DTC vector table is an array of 4-byte TI start addresses (NOT the TI blocks themselves) indexed by activation-source vector number; r_dtc_xfer_info_t models one such 16-byte TI block, which a call site places (16-byte-aligned) wherever it likes and whose address it stores into DTCVBR + vector_number*4.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_dtc_regs.h.

Enumeration Type Documentation

◆ ra8_dtc_addr_t

enum ra8_dtc_addr_t : uintptr_t

Enumerator
k_ra8_dtc_base_addr	DTC0 register block base.

Definition at line 55 of file ra8_dtc_regs.h.

◆ ra8_dtc_dtcadmod_bits_t

enum ra8_dtc_dtcadmod_bits_t : uint8_t

Enumerator
k_ra8_dtcadmod_short_msk	SHORT mode bit.

Definition at line 93 of file ra8_dtc_regs.h.

◆ ra8_dtc_dtccr_bits_t

enum ra8_dtc_dtccr_bits_t : uint8_t

Enumerator
k_ra8_dtccr_rrs_pos	DTCCR.RRS bit position.
k_ra8_dtccr_rrs_msk	DTCCR.RRS mask.
k_ra8_dtccr_reserved3	Bit 3: read-as-1 / write-as-1.
k_ra8_dtccr_rrs_disable	DTCCR with RRS=0 (FSP value).
k_ra8_dtccr_rrs_enable	DTCCR with RRS=1 (FSP value).