r_dtc_regs_t Struct Reference

DTC controller register block at 0x4000AC00. More...

#include <ra8_dtc_regs.h>

Data Fields
volatile uint8_t	DTCCR
	+0x00 Control Register (HUM 18.2.1).
volatile uint8_t	_r0
	+0x01 reserved.
volatile uint16_t	_r1
	+0x02 reserved.
volatile uint32_t	DTCVBR
	+0x04 Vector Base Register (HUM 18.2.2).
volatile uint8_t	DTCADMOD
	+0x08 Address Mode Register (HUM 18.2.12).
volatile uint8_t	_r2
	+0x09 reserved.
volatile uint16_t	_r3
	+0x0A reserved.
volatile uint8_t	DTCST
	+0x0C Module Start Register (HUM 18.2.3).
volatile uint8_t	_r4
	+0x0D reserved.
volatile uint16_t	DTCSTS
	+0x0E Status Register (HUM 18.2.4).
volatile uint8_t	DTCCR_SEC
	+0x10 Secure Control Register (HUM 18.2.5).
volatile uint8_t	_r5
	+0x11 reserved.
volatile uint16_t	_r6
	+0x12 reserved.
volatile uint32_t	DTCVBR_SEC
	+0x14 Secure Vector Base (HUM 18.2.6).
volatile uint32_t	DTCDISP
	+0x18 Address Displacement (HUM 18.2.7).
volatile uint32_t	_r7
	+0x1C reserved.
volatile uint32_t	DTEVR
	+0x20 DTC Error Vector Register (HUM 18.2.8).
volatile uint32_t	DTCIBR
	+0x24 Index Table Base Register (HUM 18.2.9).
volatile uint8_t	DTCOR
	+0x28 Operation Register (HUM 18.2.10).
volatile uint8_t	_r8
	+0x29 reserved.
volatile uint16_t	_r9
	+0x2A reserved.
volatile uint16_t	DTCSQE
	+0x2C Sequence Transfer Enable (HUM 18.2.11).
volatile uint16_t	_r10
	+0x2E reserved.

Detailed Description

DTC controller register block at 0x4000AC00.

Layout verified against FSP R_DTC_Type (R7KA8D2KF_core0.h lines 6581-6732). Total size = 0x30 bytes. Reserved members are named with an underscore prefix to keep the FSP register names directly addressable.

Definition at line 107 of file ra8_dtc_regs.h.

Field Documentation

_r0

volatile uint8_t r_dtc_regs_t::_r0

+0x01 reserved.

Definition at line 109 of file ra8_dtc_regs.h.

_r1

volatile uint16_t r_dtc_regs_t::_r1

+0x02 reserved.

Definition at line 110 of file ra8_dtc_regs.h.

_r10

volatile uint16_t r_dtc_regs_t::_r10

+0x2E reserved.

Definition at line 130 of file ra8_dtc_regs.h.

_r2

volatile uint8_t r_dtc_regs_t::_r2

+0x09 reserved.

Definition at line 113 of file ra8_dtc_regs.h.

_r3

volatile uint16_t r_dtc_regs_t::_r3

+0x0A reserved.

Definition at line 114 of file ra8_dtc_regs.h.

_r4

volatile uint8_t r_dtc_regs_t::_r4

+0x0D reserved.

Definition at line 116 of file ra8_dtc_regs.h.

_r5

volatile uint8_t r_dtc_regs_t::_r5

+0x11 reserved.

Definition at line 119 of file ra8_dtc_regs.h.

_r6

volatile uint16_t r_dtc_regs_t::_r6

+0x12 reserved.

Definition at line 120 of file ra8_dtc_regs.h.

_r7

volatile uint32_t r_dtc_regs_t::_r7

+0x1C reserved.

Definition at line 123 of file ra8_dtc_regs.h.

_r8

volatile uint8_t r_dtc_regs_t::_r8

+0x29 reserved.

Definition at line 127 of file ra8_dtc_regs.h.

_r9

volatile uint16_t r_dtc_regs_t::_r9

+0x2A reserved.

Definition at line 128 of file ra8_dtc_regs.h.

DTCADMOD

volatile uint8_t r_dtc_regs_t::DTCADMOD

+0x08 Address Mode Register (HUM 18.2.12).

Definition at line 112 of file ra8_dtc_regs.h.

DTCCR

volatile uint8_t r_dtc_regs_t::DTCCR

+0x00 Control Register (HUM 18.2.1).

Definition at line 108 of file ra8_dtc_regs.h.

Referenced by ra8_dtc_deinit(), ra8_dtc_init(), and ra8_dtc_reconfigure().

DTCCR_SEC

volatile uint8_t r_dtc_regs_t::DTCCR_SEC

+0x10 Secure Control Register (HUM 18.2.5).

Definition at line 118 of file ra8_dtc_regs.h.

DTCDISP

volatile uint32_t r_dtc_regs_t::DTCDISP

+0x18 Address Displacement (HUM 18.2.7).

Definition at line 122 of file ra8_dtc_regs.h.

DTCIBR

volatile uint32_t r_dtc_regs_t::DTCIBR

+0x24 Index Table Base Register (HUM 18.2.9).

Definition at line 125 of file ra8_dtc_regs.h.

DTCOR

volatile uint8_t r_dtc_regs_t::DTCOR

+0x28 Operation Register (HUM 18.2.10).

Definition at line 126 of file ra8_dtc_regs.h.

DTCSQE

volatile uint16_t r_dtc_regs_t::DTCSQE

+0x2C Sequence Transfer Enable (HUM 18.2.11).

Definition at line 129 of file ra8_dtc_regs.h.

DTCST

volatile uint8_t r_dtc_regs_t::DTCST

+0x0C Module Start Register (HUM 18.2.3).

Definition at line 115 of file ra8_dtc_regs.h.

Referenced by ra8_dtc_deinit(), ra8_dtc_disable(), ra8_dtc_enable(), ra8_dtc_enter_stop(), ra8_dtc_init(), and ra8_dtc_reconfigure().

DTCSTS

volatile uint16_t r_dtc_regs_t::DTCSTS

+0x0E Status Register (HUM 18.2.4).

Definition at line 117 of file ra8_dtc_regs.h.

Referenced by ra8_dtc_clear_status(), ra8_dtc_dispatch(), and ra8_dtc_get_status().

DTCVBR

volatile uint32_t r_dtc_regs_t::DTCVBR

+0x04 Vector Base Register (HUM 18.2.2).

Definition at line 111 of file ra8_dtc_regs.h.

Referenced by ra8_dtc_deinit(), ra8_dtc_init(), and ra8_dtc_reconfigure().

DTCVBR_SEC

volatile uint32_t r_dtc_regs_t::DTCVBR_SEC

+0x14 Secure Vector Base (HUM 18.2.6).

Definition at line 121 of file ra8_dtc_regs.h.

Referenced by ra8_dtc_deinit(), ra8_dtc_init(), and ra8_dtc_reconfigure().

DTEVR

volatile uint32_t r_dtc_regs_t::DTEVR

+0x20 DTC Error Vector Register (HUM 18.2.8).

Definition at line 124 of file ra8_dtc_regs.h.

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The documentation for this struct was generated from the following file:

• libs/ra8_hal/inc/ra8_dtc_regs.h