Interrupt Control Unit driver (IRQ pins, NMI). More...

#include <stdint.h>
#include "ra8_elc_regs.h"
#include "ra8_err.h"
#include "ra8_icu_regs.h"

Include dependency graph for ra8_icu.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	ra8_icu_irq_cfg_t
	One external-IRQ-pin configuration descriptor. More...

Functions
ra8_err_t	ra8_icu_init (void)
	Reset every ICU-owned register to its post-reset state.
ra8_err_t	ra8_icu_configure_irq_pin (uint8_t irq_num, const ra8_icu_irq_cfg_t *cfg)
	Programme one IRQCRi register.
ra8_err_t	ra8_icu_read_irqcr (uint8_t irq_num, uint8_t *out_val)
	Read the raw 8-bit IRQCRi value.
ra8_err_t	ra8_icu_nmi_enable (uint32_t mask)
	Enable one or more NMI sources by OR'ing into NMIER.
ra8_err_t	ra8_icu_nmi_disable (uint32_t mask)
	Disable NMI sources by clearing bits in NMIER.
ra8_err_t	ra8_icu_nmi_clear (uint32_t mask)
	Clear pending NMI status flags via NMICLR (HUM 14.2.15 p 544).
ra8_err_t	ra8_icu_nmi_status (uint32_t *out_status)
	Read the current NMISR value.

Detailed Description

Interrupt Control Unit driver (IRQ pins, NMI).

Tag: [Ring 3 / HAL] {World: S}

The low-level IELSR event allocator moved to ra8_isr; ra8_icu now owns the remaining ICU functionality:

ra8_icu_init() resets IRQCRa[0..15] + IRQCRb[0..15] (32 channels total on RA8D2, cross-checked against FSP R_ICU_Type), disables every NMI source, clears pending NMI status flags, and clears WUPEN0/WUPEN1 so no source can wake the core unexpectedly.
ra8_icu_configure_irq_pin(num, cfg) programs one of the 32 external IRQ channels (IRQCRi): edge sensitivity, digital filter clock divider, filter enable.
ra8_icu_nmi_enable(sources) / ra8_icu_nmi_disable / ra8_icu_nmi_clear manage the NMI sources mapped through NMIER / NMICR / NMICLR (HUM Ch 14 p 524..582).

All register writes go through ra8_icu_irqcr / ra8_icu_nmier accessors from ra8_icu_regs.h (HUM Ch 14 p 524).

Threading

Single-threaded init context only.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_icu.h.

Function Documentation

◆ ra8_icu_configure_irq_pin()

ra8_err_t ra8_icu_configure_irq_pin	(	uint8_t	irq_num,
		const ra8_icu_irq_cfg_t *	cfg )

nodiscard

Programme one IRQCRi register.

Writes the edge-sensitivity, filter-divider, and filter-enable fields per HUM 14.2.12 (p 535). Reserved bits in IRQCRi are always written 0 (the HUM says "should be 0" for the read-zero bits). The driver does NOT touch IELSR or enable the NVIC line – that is the ra8_isr_register responsibility.

Parameters

[in]	irq_num	IRQ channel 0..31 (IRQCRa for 0..15, IRQCRb for 16..31).
[in]	cfg	Configuration descriptor.

Returns: ra8_err_t error code.

Return values

k_ra8_ok	Register programmed.
k_ra8_err_invalid_arg	irq_num out of range.
k_ra8_err_null_ptr	cfg was NULL.

Precondition: IRQs masked or single-threaded init context.

Postcondition: IRQCR[irq_num] reflects the requested config.

Note: Per HUM 14.2.12, IRQCRi may only be rewritten while the matching IELSRn register is 0 (no event routed) – the caller must order the init sequence accordingly.; Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 76 of file ra8_icu.c.

References ra8_icu_irq_cfg_t::filter_div, ra8_icu_irq_cfg_t::filter_en, k_ra8_err_invalid_arg, k_ra8_icu_irqcr_bit_fclksel, k_ra8_icu_irqcr_mask_fclksel, k_ra8_icu_irqcr_mask_flten, k_ra8_icu_irqcr_mask_irqmd, k_ra8_icu_num_irqs, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_icu_irqcr(), ra8_log_info_val, s_tag, and ra8_icu_irq_cfg_t::sense.

Referenced by internal_attach_irq_pin(), internal_icu_extint_demo_arm(), internal_kint_demo_arm(), ra8_board_sw_attach_irq(), ra8_gpio_attach_irq(), and ra8_gpio_detach_irq().

◆ ra8_icu_init()

ra8_err_t ra8_icu_init ( void )

nodiscard

Reset every ICU-owned register to its post-reset state.

Writes 0 to IRQCRa[0..15] and IRQCRb[0..15] (all 32 RA8D2 IRQ channels), NMIER, and WUPEN0/WUPEN1, then clears every NMISR status bit via NMICLR. Does NOT touch IELSR – those slots belong to ra8_isr. Call this from early init before any driver registers an IRQ pin.

Returns: k_ra8_ok.

Precondition: Caller holds single-threaded init context.

Postcondition: IRQCRa[0..15] and IRQCRb[0..15] all read as 0.; NMIER == 0.; NMISR == 0 (all status bits cleared).; WUPEN0 == 0 and WUPEN1 == 0.

Note: Thread safety: not thread-safe.

Since: 0.1.0

Definition at line 45 of file ra8_icu.c.

References k_ra8_icu_nmiclr_all, k_ra8_icu_num_irqs, k_ra8_icu_wupen_clear, k_ra8_ok, ra8_icu_irqcr(), ra8_icu_nmiclr(), ra8_icu_nmier(), ra8_icu_wupen0(), ra8_icu_wupen1(), ra8_log_info, and s_tag.

Referenced by internal_icu_extint_demo_setup_or_halt(), and internal_kint_demo_setup_or_halt().

◆ ra8_icu_nmi_clear()

ra8_err_t ra8_icu_nmi_clear ( uint32_t mask )

nodiscard

Clear pending NMI status flags via NMICLR (HUM 14.2.15 p 544).

Parameters

[in] mask Bit mask of NMICLR bits to set (write-1-to-clear).

Returns: k_ra8_ok.

Precondition: IRQs masked or single-threaded init context.

Postcondition: The targeted NMISR bits read as 0.

Since: 0.1.0

Definition at line 135 of file ra8_icu.c.

References k_ra8_ok, and ra8_icu_nmiclr().

Referenced by ra8_wdt_install_nmi(), and ra8_wdt_uninstall_nmi().

◆ ra8_icu_nmi_disable()

ra8_err_t ra8_icu_nmi_disable ( uint32_t mask )

nodiscard

Disable NMI sources by clearing bits in NMIER.

Parameters

[in] mask Bit mask to clear in NMIER (21 bits, FSP R_ICU_NMIER).

Returns: k_ra8_ok.

Precondition: IRQs masked or single-threaded init context.

Postcondition: NMIER has the requested bits clear.

Since: 0.1.0

Definition at line 127 of file ra8_icu.c.

References k_ra8_ok, and ra8_icu_nmier().

Referenced by ra8_wdt_uninstall_nmi().

◆ ra8_icu_nmi_enable()

ra8_err_t ra8_icu_nmi_enable ( uint32_t mask )

nodiscard

Enable one or more NMI sources by OR'ing into NMIER.

The NMIER layout is source-specific; pass a mask of the bits that correspond to the sources the caller wants enabled. HUM 14.2.14 (p 542) lists the bit assignments.

Parameters

[in] mask Bit mask to OR into NMIER.

Returns: k_ra8_ok.

Precondition: IRQs masked or single-threaded init context.

Postcondition: NMIER has the requested bits set.

Note: NMIER bits are sticky-set – to disable, rewrite the register via ra8_icu_nmi_disable.

Since: 0.1.0

Definition at line 119 of file ra8_icu.c.

References k_ra8_ok, and ra8_icu_nmier().

Referenced by ra8_wdt_install_nmi().

◆ ra8_icu_nmi_status()

ra8_err_t ra8_icu_nmi_status ( uint32_t * out_status )

nodiscard

Read the current NMISR value.

Parameters

[out] out_status NMISR value on success (32-bit).

Returns: k_ra8_ok or k_ra8_err_null_ptr.

Precondition: out_status is non-NULL.

Postcondition: No hardware state is modified.

Since: 0.1.0

Definition at line 142 of file ra8_icu.c.

References k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_icu_nmisr(), and s_tag.

◆ ra8_icu_read_irqcr()

ra8_err_t ra8_icu_read_irqcr	(	uint8_t	irq_num,
		uint8_t *	out_val )

nodiscard

Read the raw 8-bit IRQCRi value.

Parameters

[in]	irq_num	Pin 0..31.
[out]	out_val	On success, the current register value.

Returns: k_ra8_ok on success, k_ra8_err_invalid_arg on out-of-range pin, or k_ra8_err_null_ptr.

Precondition: out_val is non-NULL.

Postcondition: No hardware state is modified.

Since: 0.1.0

Definition at line 100 of file ra8_icu.c.

References k_ra8_err_invalid_arg, k_ra8_icu_num_irqs, k_ra8_ok, RA8_CHECK_NULL_PTR, ra8_icu_irqcr(), and s_tag.

Referenced by main().

Data Structures

Functions

Detailed Description

Threading

Function Documentation

◆ ra8_icu_configure_irq_pin()

◆ ra8_icu_init()

◆ ra8_icu_nmi_clear()

◆ ra8_icu_nmi_disable()

◆ ra8_icu_nmi_enable()

◆ ra8_icu_nmi_status()

◆ ra8_icu_read_irqcr()