JTAG / IEEE-1149.1 Boundary Scan TAP constants for the RA8D2. More...

#include <stdint.h>

Include dependency graph for ra8_bscan_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_bscan_width_t : uint8_t { k_ra8_bscan_jtir_bits = 4U , k_ra8_bscan_jtidr_bits = 32U , k_ra8_bscan_jtbpr_bits = 1U }
	Bit-widths of the four JTAG TAP registers. More...
enum	ra8_bscan_reset_t : uint32_t { k_ra8_bscan_jtir_reset = 0x0EU , k_ra8_bscan_jtidr_reset = 0x085DA447UL }
	Power-on-reset values of the JTAG registers. More...
enum	ra8_bscan_instr_t : uint8_t { k_ra8_bscan_instr_extest = 0x0U , k_ra8_bscan_instr_sample_preload = 0x1U , k_ra8_bscan_instr_idcode = 0x3U , k_ra8_bscan_instr_clamp = 0x5U , k_ra8_bscan_instr_highz = 0x6U , k_ra8_bscan_instr_bypass = 0xFU }
	JTIR Test Bit Set (TS[3:0]) command codes. More...
enum	ra8_bscan_pin_t : uint8_t { k_ra8_bscan_pin_tck = 0U , k_ra8_bscan_pin_tms = 1U , k_ra8_bscan_pin_tdi = 2U , k_ra8_bscan_pin_tdo = 3U , k_ra8_bscan_pin_count = 4U }
	JTAG TAP pin role identifiers. More...

Detailed Description

JTAG / IEEE-1149.1 Boundary Scan TAP constants for the RA8D2.

The RA8D2 implements an IEEE-1149.1 (JTAG) Test Access Port for manufacturing-test boundary scan. Per HUM Ch 50 "Boundary Scan", p 3257-3262, the four TAP registers –

JTIR : Instruction Register (4-bit, reset value 0xE = BYPASS)
JTIDR : ID Code Register (32-bit, fixed 0x085D_A447)
JTBPR : Bypass Register (1-bit, undefined after reset)
JTBSR : Boundary Scan Register (BSDL-defined, undefined after reset)

– are NOT memory-mapped into the CPU's address space. They are accessed exclusively through the TDI/TDO serial chain by an external JTAG controller while the device is held in reset (RES driven low). The HUM is explicit (Ch 50.2.3, p 3259): "The JTBPR register cannot be read from or written to by the CPU." The same applies to JTIR / JTIDR / JTBSR.

Consequently this "regs" header does not declare a register struct or accessor function (there is nothing the CPU can read at a known address). It instead exposes the JTAG-side constants – instruction opcodes, expected ID code, reset values, register widths – that firmware needs to validate / report the TAP configuration to a host tool that drives the actual scan vectors over the four JTAG pins.

The driver in ra8_bscan.c keeps a small CPU-side state object (initialized / not-initialized, last-instruction-loaded if the host tool tells us, expected ID code) so a unit test can exercise the lifecycle and constant-equivalence checks even though it cannot exercise an actual scan.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_bscan_regs.h.

Enumeration Type Documentation

◆ ra8_bscan_instr_t

enum ra8_bscan_instr_t : uint8_t

JTIR Test Bit Set (TS[3:0]) command codes.

From the JTIR register description in HUM Ch 50.2.1 (p 3258). All other 4-bit values are reserved. The driver validates that any caller-supplied "current instruction" is one of these named values before recording it in its state object.

Enumerator
k_ra8_bscan_instr_extest	External test mode.
k_ra8_bscan_instr_sample_preload	Sample / preload.
k_ra8_bscan_instr_idcode	Read JTIDR (Renesas code).
k_ra8_bscan_instr_clamp	Clamp output pins.
k_ra8_bscan_instr_highz	High-impedance output.
k_ra8_bscan_instr_bypass	Bypass register selected.

Definition at line 108 of file ra8_bscan_regs.h.

◆ ra8_bscan_pin_t

enum ra8_bscan_pin_t : uint8_t

JTAG TAP pin role identifiers.

From HUM Table 50.2 "Boundary scan I/O pins" (p 3257). These are exposed as named constants so debug logs and BSDL-driven host tooling can reference the pins by symbolic role rather than by package pin number (which differs per package variant).

Note: The RA8D2 does not implement the optional TRST pin (HUM Ch 50.1 note, p 3257), so reset of the TAP must be performed by holding TMS=1 for at least 5 TCK clocks.

Enumerator
k_ra8_bscan_pin_tck	Test clock input.
k_ra8_bscan_pin_tms	Test mode select.
k_ra8_bscan_pin_tdi	Test data input.
k_ra8_bscan_pin_tdo	Test data output.
k_ra8_bscan_pin_count	Number of TAP pins.

Definition at line 136 of file ra8_bscan_regs.h.

◆ ra8_bscan_reset_t

enum ra8_bscan_reset_t : uint32_t

Power-on-reset values of the JTAG registers.

From HUM Table 50.3 (p 3258). JTBPR / JTBSR are explicitly listed as "Undefined" after reset and so are not modelled as constants here. JTIR resets to 0xE – which is in the "Reserved" rows of the TS[3:0] decode table (p 3258), one nibble below the BYPASS opcode. The TAP controller forces the BYPASS path on reset regardless of the raw 0xE bit pattern; the test harness only needs the literal reset value when reading back the register through Shift-IR for verification.

Enumerator
k_ra8_bscan_jtir_reset	JTIR reset value.
k_ra8_bscan_jtidr_reset	JTIDR fixed device ID.

Definition at line 88 of file ra8_bscan_regs.h.

◆ ra8_bscan_width_t

enum ra8_bscan_width_t : uint8_t

Bit-widths of the four JTAG TAP registers.

Sourced from HUM Table 50.3 "Boundary scan registers" (p 3258) and the bit-position diagrams of JTIR (p 3258) and JTIDR (p 3258-3259). JTBSR is BSDL-defined and varies per package; the device ships a BSDL file separately and the scan length is not fixed by the chip.

Enumerator
k_ra8_bscan_jtir_bits	JTIR is 4 bits wide (TS[3:0]).
k_ra8_bscan_jtidr_bits	JTIDR is 32 bits wide (DID[31:0]).
k_ra8_bscan_jtbpr_bits	JTBPR is a single bit shift register.

Definition at line 63 of file ra8_bscan_regs.h.