ra8_pdg_regs.h File Reference

PWM Delay Generation Circuit (PDG) register layout for the Renesas RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

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Data Structures
struct	r_pdg_dly_pair_t
	Two consecutive 16-bit delay cells that match the PDG layout. More...
struct	r_pdg_regs_t
	PDG block register window mapped at k_ra8_pdg_base_addr. More...

Enumerations
enum	ra8_pdg_addr_t : uintptr_t {   k_ra8_pdg_base_addr = 0x40324000UL ,   k_ra8_pdg_ns_base_addr = 0x50324000UL }
	Memory-mapped base addresses for the PDG block. More...
enum	ra8_pdg_off_t : uintptr_t {   k_ra8_pdg_off_gtdlycr = 0x000U ,   k_ra8_pdg_off_gtdlycr2 = 0x002U ,   k_ra8_pdg_off_gtdlyr0a = 0x018U ,   k_ra8_pdg_off_gtdlyr0b = 0x01AU ,   k_ra8_pdg_off_gtdlyf0a = 0x028U ,   k_ra8_pdg_off_gtdlyf0b = 0x02AU }
	Byte offsets of PDG registers (HUM Ch 23.2.1..23.2.6). More...
enum	ra8_pdg_count_t : uint8_t {   k_ra8_pdg_channel_count = 4U ,   k_ra8_pdg_pin_count = 2U ,   k_ra8_pdg_edge_count = 2U ,   k_ra8_pdg_slot_count = 16U ,   k_ra8_pdg_off_gtdlyr0 = 0x18U ,   k_ra8_pdg_off_after_cr2 = 0x4U }
	Channel count and per-channel structural sizes. More...
enum	ra8_pdg_gtdlycr_bit_t : uint8_t {   k_ra8_pdg_gtdlycr_bit_dllen = 0U ,   k_ra8_pdg_gtdlycr_bit_dlyrst = 1U ,   k_ra8_pdg_gtdlycr_shift_frange = 8U }
	Bit positions inside GTDLYCR (HUM Ch 23.2.1 p 1154). More...
enum	ra8_pdg_gtdlycr_mask_t : uint16_t {   k_ra8_pdg_gtdlycr_mask_dllen ,   k_ra8_pdg_gtdlycr_mask_dlyrst ,   k_ra8_pdg_gtdlycr_mask_frange }
	Masks for GTDLYCR fields. More...
enum	ra8_pdg_frange_t : uint8_t {   k_ra8_pdg_frange_80_160_mhz = 0x0U ,   k_ra8_pdg_frange_155_300_mhz = 0x1U ,   k_ra8_pdg_frange_invalid = 0x3U }
	GTDLYCR.FRANGE encoding (HUM Ch 23.2.1 p 1154). More...
enum	ra8_pdg_gtdlycr2_shift_t : uint8_t {   k_ra8_pdg_gtdlycr2_shift_dlybs = 0U ,   k_ra8_pdg_gtdlycr2_shift_dlyen = 8U }
	Bit positions for GTDLYCR2 fields (HUM Ch 23.2.2 p 1155). More...
enum	ra8_pdg_gtdlycr2_mask_t : uint16_t {   k_ra8_pdg_gtdlycr2_mask_dlybs ,   k_ra8_pdg_gtdlycr2_mask_dlyen }
	Masks for GTDLYCR2 fields. More...
enum	ra8_pdg_dly_field_t : uint16_t {   k_ra8_pdg_dly_mask = 0x007FU ,   k_ra8_pdg_dly_max = 0x007FU ,   k_ra8_pdg_dly_div_low = 128U ,   k_ra8_pdg_dly_div_high = 64U }
	Layout of the GTDLYRnA / GTDLYRnB / GTDLYFnA / GTDLYFnB delay registers (HUM Ch 23.2.3..23.2.6 p 1156-1158). More...
enum	ra8_pdg_freq_band_t : uint32_t {   k_ra8_pdg_freq_low_min_hz = 80000000UL ,   k_ra8_pdg_freq_low_max_hz = 160000000UL ,   k_ra8_pdg_freq_high_min_hz = 155000000UL ,   k_ra8_pdg_freq_high_max_hz = 300000000UL ,   k_ra8_pdg_freq_overlap_top = 160000000UL ,   k_ra8_pdg_freq_overlap_bot = 155000000UL }
	Per-band absolute frequency boundaries (Hz) for FRANGE. More...

Functions
static volatile r_pdg_regs_t *	ra8_pdg (void)
	Pointer to the PDG block.

Detailed Description

PWM Delay Generation Circuit (PDG) register layout for the Renesas RA8D2.

The PDG block (HUM Ch 23 "PWM Delay Generation Circuit (PDG)", p 1152-1163) is the per-edge fine-delay engine that sits between GPT320..GPT323 and the GTIOC0..GTIOC3 output pads. It provides a DLL-based delay line capable of shifting the rising and falling edges of each PWM channel by an integer fraction (1/64 or 1/128) of the GPT core clock (GTCLK) period.

The block exposes the following registers (HUM Ch 23.2):

Offset	Reg	Width	Purpose
0x000	GTDLYCR	16	DLL enable, reset, frequency range select
0x002	GTDLYCR2	16	Per-channel bypass + per-channel power enable
0x018	GTDLYR0A	16	Channel 0 GTIOCnA rising-edge delay code (DLY[6:0])
0x01C	GTDLYR1A	16	Channel 1 GTIOCnA rising-edge delay code
0x020	GTDLYR2A	16	Channel 2 GTIOCnA rising-edge delay code
0x024	GTDLYR3A	16	Channel 3 GTIOCnA rising-edge delay code
0x01A	GTDLYR0B	16	Channel 0 GTIOCnB rising-edge delay code
0x01E	GTDLYR1B	16	Channel 1 GTIOCnB rising-edge delay code
0x022	GTDLYR2B	16	Channel 2 GTIOCnB rising-edge delay code
0x026	GTDLYR3B	16	Channel 3 GTIOCnB rising-edge delay code
0x028	GTDLYF0A	16	Channel 0 GTIOCnA falling-edge delay code
0x02C	GTDLYF1A	16	Channel 1 GTIOCnA falling-edge delay code
0x030	GTDLYF2A	16	Channel 2 GTIOCnA falling-edge delay code
0x034	GTDLYF3A	16	Channel 3 GTIOCnA falling-edge delay code
0x02A	GTDLYF0B	16	Channel 0 GTIOCnB falling-edge delay code
0x02E	GTDLYF1B	16	Channel 1 GTIOCnB falling-edge delay code
0x032	GTDLYF2B	16	Channel 2 GTIOCnB falling-edge delay code
0x036	GTDLYF3B	16	Channel 3 GTIOCnB falling-edge delay code

The base address per HUM Ch 23.2.1 (p 1154) is PDG = 0x4032_4000 (Secure alias) / PDG_NS = 0x5032_4000 (Non-Secure alias). Only the Secure alias is exposed here; the driver targets the Secure world.

Register addresses for GTDLYRnA / GTDLYRnB / GTDLYFnA / GTDLYFnB follow the formulas in HUM Ch 23.2.3..23.2.6 (p 1156-1158):

GTDLYRnA -> 0x018 + 0x4 * n GTDLYRnB -> 0x01A + 0x4 * n GTDLYFnA -> 0x028 + 0x4 * n GTDLYFnB -> 0x02A + 0x4 * n

The struct laid out below uses an array of two 16-bit cells per channel grouped by edge so the formula collapses to a clean dly_rise[n].A / dly_fall[n].B index.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_pdg_regs.h.

Enumeration Type Documentation

ra8_pdg_addr_t

enum ra8_pdg_addr_t : uintptr_t

Memory-mapped base addresses for the PDG block.

Cited from HUM Ch 23.2.1 "GTDLYCR : PWM Output Delay Control Register" p 1154. Both PDG (Secure) and PDG_NS (Non-Secure) aliases exist; this driver targets PDG. Use uintptr_t so the value is portable between the 32-bit RA8D2 target and the 64-bit x86_64 host test build.

Enumerator
k_ra8_pdg_base_addr	PDG Secure alias.
k_ra8_pdg_ns_base_addr	PDG Non-Secure alias.

Definition at line 79 of file ra8_pdg_regs.h.

ra8_pdg_count_t

enum ra8_pdg_count_t : uint8_t

Channel count and per-channel structural sizes.

The PDG drives 4 GPT channels (HUM Ch 23.1 p 1152). Each channel has 2 output pins (GTIOCnA / GTIOCnB) and 2 edges (rising / falling), giving 4 * 2 * 2 = 16 individual delay codes. The "edge slot count" field is used by the batch-update API to size its per-call descriptor array.

Enumerator
k_ra8_pdg_channel_count	4 GPT channels mapped to PDG (0..3).
k_ra8_pdg_pin_count	GTIOCnA + GTIOCnB.
k_ra8_pdg_edge_count	Rising + falling delay slots.
k_ra8_pdg_slot_count	4 ch * 2 pin * 2 edge = 16 delay slots.
k_ra8_pdg_off_gtdlyr0	First GTDLYR offset (rises).
k_ra8_pdg_off_after_cr2	End of GTDLYCR2 (start of reserved gap).

Definition at line 116 of file ra8_pdg_regs.h.

ra8_pdg_dly_field_t

enum ra8_pdg_dly_field_t : uint16_t

Layout of the GTDLYRnA / GTDLYRnB / GTDLYFnA / GTDLYFnB delay registers (HUM Ch 23.2.3..23.2.6 p 1156-1158).

Only DLY[6:0] is software-writable; bits [15:7] read as 0 and must be written as 0. Allowed code range is 0x00..0x7F. Code 0x00 disables the per-edge delay; the meaning of the remaining codes depends on FRANGE (1/128 step in the low band, 1/64 step in the high band).

Enumerator
k_ra8_pdg_dly_mask	DLY[6:0] occupies the low 7 bits.
k_ra8_pdg_dly_max	Maximum legal delay code.
k_ra8_pdg_dly_div_low	Divider in the 80..160 MHz band.
k_ra8_pdg_dly_div_high	Divider in the 155..300 MHz band.

Definition at line 219 of file ra8_pdg_regs.h.

ra8_pdg_frange_t

enum ra8_pdg_frange_t : uint8_t

GTDLYCR.FRANGE encoding (HUM Ch 23.2.1 p 1154).

The DLL needs to know the rough GTCLK band to pick its tap count. The lower band gives 1/128 resolution; the upper band runs at 1/64 resolution because the DLL halves its tap count.

Enumerator
k_ra8_pdg_frange_80_160_mhz	80..160 MHz, 1/128 step.
k_ra8_pdg_frange_155_300_mhz	155..300 MHz, 1/64 step.
k_ra8_pdg_frange_invalid	0b11 – "Setting prohibited" sentinel.

Definition at line 168 of file ra8_pdg_regs.h.

ra8_pdg_freq_band_t

enum ra8_pdg_freq_band_t : uint32_t

Per-band absolute frequency boundaries (Hz) for FRANGE.

Used by the auto-tune helper to pick a FRANGE value automatically. Boundaries reproduced verbatim from HUM Ch 23.2.1 p 1154.

Enumerator
k_ra8_pdg_freq_low_min_hz	80 MHz.
k_ra8_pdg_freq_low_max_hz	160 MHz.
k_ra8_pdg_freq_high_min_hz	155 MHz.
k_ra8_pdg_freq_high_max_hz	300 MHz.
k_ra8_pdg_freq_overlap_top	Top of the overlap zone.
k_ra8_pdg_freq_overlap_bot	Bottom of overlap zone.

Definition at line 235 of file ra8_pdg_regs.h.

ra8_pdg_gtdlycr2_mask_t

enum ra8_pdg_gtdlycr2_mask_t : uint16_t

Masks for GTDLYCR2 fields.

Enumerator
k_ra8_pdg_gtdlycr2_mask_dlybs	RA8 pdg gtdlycr2 mask dlybs.
k_ra8_pdg_gtdlycr2_mask_dlyen	RA8 pdg gtdlycr2 mask dlyen.

Definition at line 197 of file ra8_pdg_regs.h.

ra8_pdg_gtdlycr2_shift_t

enum ra8_pdg_gtdlycr2_shift_t : uint8_t

Bit positions for GTDLYCR2 fields (HUM Ch 23.2.2 p 1155).

• DLYBS0..DLYBS3 occupy bits [3:0] (1 = delay applied, 0 = bypass).
• DLYEN0..DLYEN3 occupy bits [11:8] (0 = power-on, 1 = power-off).

Note the inverted polarity of DLYEN: the bit set means "disabled". The driver hides this in its API (exit_stop clears the bit, enter_stop sets it).

Enumerator
k_ra8_pdg_gtdlycr2_shift_dlybs	DLYBS field starts at bit 0.
k_ra8_pdg_gtdlycr2_shift_dlyen	DLYEN field starts at bit 8.

Definition at line 187 of file ra8_pdg_regs.h.

ra8_pdg_gtdlycr_bit_t

enum ra8_pdg_gtdlycr_bit_t : uint8_t

Bit positions inside GTDLYCR (HUM Ch 23.2.1 p 1154).

• DLLEN @ bit 0 – enable on-chip DLL.
• DLYRST @ bit 1 – 1 = circuit held in reset, 0 = normal.
• FRANGE[1:0] @ bits [9:8] – GPT core clock frequency band. 00b = 80..160 MHz, 01b = 155..300 MHz; other codes are "Setting prohibited" (HUM 23.2.1 p 1154).

Enumerator
k_ra8_pdg_gtdlycr_bit_dllen	DLL Operation Enable.
k_ra8_pdg_gtdlycr_bit_dlyrst	PDG circuit reset.
k_ra8_pdg_gtdlycr_shift_frange	FRANGE[1:0] starts at bit 8.

Definition at line 137 of file ra8_pdg_regs.h.

ra8_pdg_gtdlycr_mask_t

enum ra8_pdg_gtdlycr_mask_t : uint16_t

Masks for GTDLYCR fields.

Enumerator
k_ra8_pdg_gtdlycr_mask_dllen	RA8 pdg gtdlycr mask dllen.
k_ra8_pdg_gtdlycr_mask_dlyrst	RA8 pdg gtdlycr mask dlyrst.
k_ra8_pdg_gtdlycr_mask_frange	RA8 pdg gtdlycr mask frange.

Definition at line 148 of file ra8_pdg_regs.h.

ra8_pdg_off_t

enum ra8_pdg_off_t : uintptr_t

Byte offsets of PDG registers (HUM Ch 23.2.1..23.2.6).

GTDLYRnA / GTDLYRnB / GTDLYFnA / GTDLYFnB obey base + 0x4 * n indexing inside the channel groups; the four "channel 0" offsets are listed here so consumers that prefer raw offsets do not have to recompute them.

Enumerator
k_ra8_pdg_off_gtdlycr	Delay control reg.
k_ra8_pdg_off_gtdlycr2	Bypass / enable reg.
k_ra8_pdg_off_gtdlyr0a	Ch0 GTIOCnA rise.
k_ra8_pdg_off_gtdlyr0b	Ch0 GTIOCnB rise.
k_ra8_pdg_off_gtdlyf0a	Ch0 GTIOCnA fall.
k_ra8_pdg_off_gtdlyf0b	Ch0 GTIOCnB fall.

Definition at line 95 of file ra8_pdg_regs.h.

Function Documentation

ra8_pdg()

volatile r_pdg_regs_t * ra8_pdg ( void )

inlinestatic

Pointer to the PDG block.

Returns

Volatile pointer at k_ra8_pdg_base_addr.

Precondition

Pointer cast must observe the host-vs-target uintptr_t width.

Caller has cleared the PDG module-stop bit (MSTPD6).

Postcondition

Return value is non-null.

Subsequent dereferences see live PDG state.

Note

Re-entrancy: returns the same pointer on every call.

Since

0.1.0

Definition at line 301 of file ra8_pdg_regs.h.

References k_ra8_pdg_base_addr.

Referenced by internal_dly_cell(), internal_pdg_is_initialized(), internal_program_dll(), ra8_pdg_channel_bypass_set(), ra8_pdg_clear_status(), ra8_pdg_deinit(), ra8_pdg_enter_stop(), ra8_pdg_exit_stop(), ra8_pdg_get_status(), ra8_pdg_get_status_full(), and ra8_pdg_set_frange().