ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_pdg_regs_t Struct Reference

PDG block register window mapped at k_ra8_pdg_base_addr. More...

#include <ra8_pdg_regs.h>

Collaboration diagram for r_pdg_regs_t:

Data Fields

volatile uint16_t GTDLYCR
 +0x000 HUM 23.2.1 p 1154
volatile uint16_t GTDLYCR2
 +0x002 HUM 23.2.2 p 1155
volatile uint8_t reserved_004 [k_ra8_pdg_off_gtdlyr0 - k_ra8_pdg_off_after_cr2]
 +0x004..0x017 reserved.
r_pdg_dly_pair_t GTDLYR [k_ra8_pdg_channel_count]
 +0x018..0x027 rise.
r_pdg_dly_pair_t GTDLYF [k_ra8_pdg_channel_count]
 +0x028..0x037 fall.

Detailed Description

PDG block register window mapped at k_ra8_pdg_base_addr.

Field offsets verified against HUM Ch 23.2 (p 1154-1158):

  • GTDLYCR @ 0x000 (16-bit)
  • GTDLYCR2 @ 0x002 (16-bit)
  • reserved 0x004..0x017 (20 bytes)
  • GTDLYR[0..3] @ 0x018..0x027 (4 channels, A+B per channel)
  • GTDLYF[0..3] @ 0x028..0x037 (4 channels, A+B per channel)

The reserved gap is modelled as a fixed-size byte filler so the subsequent arrays land at exactly the HUM-specified offset.

Definition at line 278 of file ra8_pdg_regs.h.

Field Documentation

◆ GTDLYCR

volatile uint16_t r_pdg_regs_t::GTDLYCR

◆ GTDLYCR2

volatile uint16_t r_pdg_regs_t::GTDLYCR2

◆ GTDLYF

+0x028..0x037 fall.

Definition at line 284 of file ra8_pdg_regs.h.

Referenced by internal_dly_cell(), and ra8_pdg_deinit().

◆ GTDLYR

+0x018..0x027 rise.

Definition at line 283 of file ra8_pdg_regs.h.

Referenced by internal_dly_cell(), and ra8_pdg_deinit().

◆ reserved_004

volatile uint8_t r_pdg_regs_t::reserved_004[k_ra8_pdg_off_gtdlyr0 - k_ra8_pdg_off_after_cr2]

+0x004..0x017 reserved.

Definition at line 282 of file ra8_pdg_regs.h.


The documentation for this struct was generated from the following file: