r_pdg_dly_pair_t Struct Reference

Two consecutive 16-bit delay cells that match the PDG layout. More...

#include <ra8_pdg_regs.h>

Data Fields
volatile uint16_t	A
	+0 GTIOCnA delay code (DLY[6:0]).
volatile uint16_t	B
	+2 GTIOCnB delay code (DLY[6:0]).

Detailed Description

Two consecutive 16-bit delay cells that match the PDG layout.

The HUM lays out the delay registers as four interleaved sets: GTDLYRnA / GTDLYRnB / GTDLYFnA / GTDLYFnB. Inside each set the channel index n strides by 4 bytes, and the A / B pin variants of the same channel are 2 bytes apart. Wrapping the pair into a struct lets us index it as dly_rise[n].A / dly_rise[n].B which matches the FSP register-block convention.

Definition at line 256 of file ra8_pdg_regs.h.

Field Documentation

A

volatile uint16_t r_pdg_dly_pair_t::A

+0 GTIOCnA delay code (DLY[6:0]).

Definition at line 257 of file ra8_pdg_regs.h.

Referenced by internal_dly_cell(), and ra8_pdg_deinit().

B

volatile uint16_t r_pdg_dly_pair_t::B

+2 GTIOCnB delay code (DLY[6:0]).

Definition at line 258 of file ra8_pdg_regs.h.

Referenced by internal_dly_cell(), and ra8_pdg_deinit().

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The documentation for this struct was generated from the following file:

• libs/ra8_hal/inc/ra8_pdg_regs.h