ra8_pdg_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

/* HUM Ch 23.2.1 "GTDLYCR : PWM Output Delay Control Register" p 1154 */
typedef enum : uintptr_t {
  k_ra8_pdg_base_addr    = 0x40324000UL, 
  k_ra8_pdg_ns_base_addr = 0x50324000UL, 
} ra8_pdg_addr_t;

/* HUM Ch 23.2 "Register Descriptions" p 1154-1158 */
typedef enum : uintptr_t {
  k_ra8_pdg_off_gtdlycr  = 0x000U, 
  k_ra8_pdg_off_gtdlycr2 = 0x002U, 
  k_ra8_pdg_off_gtdlyr0a = 0x018U, 
  k_ra8_pdg_off_gtdlyr0b = 0x01AU, 
  k_ra8_pdg_off_gtdlyf0a = 0x028U, 
  k_ra8_pdg_off_gtdlyf0b = 0x02AU, 
} ra8_pdg_off_t;

/* HUM Ch 23.1 "Overview" p 1152 */
typedef enum : uint8_t {
  k_ra8_pdg_channel_count = 4U,    
  k_ra8_pdg_pin_count     = 2U,    
  k_ra8_pdg_edge_count    = 2U,    
  k_ra8_pdg_slot_count    = 16U,   
  k_ra8_pdg_off_gtdlyr0   = 0x18U, 
  k_ra8_pdg_off_after_cr2 = 0x4U,  
} ra8_pdg_count_t;

/* HUM Ch 23.2.1 "GTDLYCR : PWM Output Delay Control Register" p 1154 */
typedef enum : uint8_t {
  k_ra8_pdg_gtdlycr_bit_dllen    = 0U, 
  k_ra8_pdg_gtdlycr_bit_dlyrst   = 1U, 
  k_ra8_pdg_gtdlycr_shift_frange = 8U, 
} ra8_pdg_gtdlycr_bit_t;

/* HUM Ch 23.2.1 "GTDLYCR" p 1154 */
typedef enum : uint16_t {
  k_ra8_pdg_gtdlycr_mask_dllen =
    (uint16_t)(1U << (uint16_t)k_ra8_pdg_gtdlycr_bit_dllen), 
  k_ra8_pdg_gtdlycr_mask_dlyrst =
    (uint16_t)(1U << (uint16_t)k_ra8_pdg_gtdlycr_bit_dlyrst), 
  k_ra8_pdg_gtdlycr_mask_frange =
    (uint16_t)(0x3U << (uint16_t)
                 k_ra8_pdg_gtdlycr_shift_frange), 
} ra8_pdg_gtdlycr_mask_t;

/* HUM Ch 23.2.1 "GTDLYCR" p 1154 */
typedef enum : uint8_t {
  k_ra8_pdg_frange_80_160_mhz  = 0x0U, 
  k_ra8_pdg_frange_155_300_mhz = 0x1U, 
  k_ra8_pdg_frange_invalid     = 0x3U, 
} ra8_pdg_frange_t;

/* HUM Ch 23.2.2 "GTDLYCR2" p 1155 */
typedef enum : uint8_t {
  k_ra8_pdg_gtdlycr2_shift_dlybs = 0U, 
  k_ra8_pdg_gtdlycr2_shift_dlyen = 8U, 
} ra8_pdg_gtdlycr2_shift_t;

/* HUM Ch 23.2.2 "GTDLYCR2" p 1155 */
typedef enum : uint16_t {
  k_ra8_pdg_gtdlycr2_mask_dlybs =
    (uint16_t)(0xFU << (uint16_t)
                 k_ra8_pdg_gtdlycr2_shift_dlybs), 
  k_ra8_pdg_gtdlycr2_mask_dlyen =
    (uint16_t)(0xFU << (uint16_t)
                 k_ra8_pdg_gtdlycr2_shift_dlyen), 
} ra8_pdg_gtdlycr2_mask_t;

/* HUM Ch 23.2.3 "GTDLYRnA" p 1156 */
typedef enum : uint16_t {
  k_ra8_pdg_dly_mask     = 0x007FU, 
  k_ra8_pdg_dly_max      = 0x007FU, 
  k_ra8_pdg_dly_div_low  = 128U,    
  k_ra8_pdg_dly_div_high = 64U,     
} ra8_pdg_dly_field_t;

/* HUM Ch 23.2.1 "GTDLYCR" p 1154 */
typedef enum : uint32_t {
  k_ra8_pdg_freq_low_min_hz  = 80000000UL,  
  k_ra8_pdg_freq_low_max_hz  = 160000000UL, 
  k_ra8_pdg_freq_high_min_hz = 155000000UL, 
  k_ra8_pdg_freq_high_max_hz = 300000000UL, 
  k_ra8_pdg_freq_overlap_top = 160000000UL, 
  k_ra8_pdg_freq_overlap_bot = 155000000UL, 
} ra8_pdg_freq_band_t;

typedef struct {
  volatile uint16_t A; 
  volatile uint16_t B; 
} r_pdg_dly_pair_t;

/* HUM Ch 23.2 "Register Descriptions" p 1154-1158 */
typedef struct {
  volatile uint16_t GTDLYCR;  
  volatile uint16_t GTDLYCR2; 
  volatile uint8_t
    reserved_004[k_ra8_pdg_off_gtdlyr0 - k_ra8_pdg_off_after_cr2]; 
  r_pdg_dly_pair_t GTDLYR[k_ra8_pdg_channel_count];                
  r_pdg_dly_pair_t GTDLYF[k_ra8_pdg_channel_count];                
} r_pdg_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_pdg_regs_t* ra8_pdg(void)
{
  return (volatile r_pdg_regs_t*)k_ra8_pdg_base_addr;
}
 
#ifdef __cplusplus
}
#endif