Inter-Processor Communication (IPC) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_ipc_regs.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	r_ipc_channel_regs_t
	Per-FIFO-channel register window (5 x 32-bit at +0x20 stride). More...
struct	r_ipc_nmi_regs_t
	Per-NMI-unit register window (3 x 32-bit at +0x10 stride). More...

Enumerations
enum	ra8_ipc_addr_t : uintptr_t { k_ra8_ipc_base_addr = 0x40020000UL , k_ra8_ipc_cpscu_addr = 0x40008000UL , k_ra8_ipc_ipcsar_addr = 0x40008610UL , k_ra8_ipc_ipcpar_addr = 0x40008614UL }
	Memory-mapped base addresses for the IPC block and the CPSCU window that holds IPCSAR / IPCPAR. More...
enum	ra8_ipc_offset_t : uint16_t { k_ra8_ipc_offset_ipcsem0 = 0x000U , k_ra8_ipc_offset_ipcsem15 = 0x03CU , k_ra8_ipc_offset_ipc0nmista = 0x080U , k_ra8_ipc_offset_ipc0nmiset = 0x084U , k_ra8_ipc_offset_ipc0nmiclr = 0x088U , k_ra8_ipc_offset_ipc1nmista = 0x090U , k_ra8_ipc_offset_ipc1nmiset = 0x094U , k_ra8_ipc_offset_ipc1nmiclr = 0x098U , k_ra8_ipc_offset_ipc0_ch0 = 0x0C0U , k_ra8_ipc_offset_ipc0_ch1 = 0x0E0U , k_ra8_ipc_offset_ipc1_ch0 = 0x100U , k_ra8_ipc_offset_ipc1_ch1 = 0x120U }
	In-block offsets relative to k_ra8_ipc_base_addr. More...
enum	ra8_ipc_limits_t : uint8_t { k_ra8_ipc_sem_count = 16U , k_ra8_ipc_nmi_unit_count = 2U , k_ra8_ipc_channel_count = 4U , k_ra8_ipc_irq_event_count = 8U , k_ra8_ipc_fifo_depth = 4U , k_ra8_ipc_channel_stride = 0x20U , k_ra8_ipc_nmi_stride = 0x10U }
	Counts and strides used by the driver / accessors. More...
enum	ra8_ipc_unit_id_t : uint8_t { k_ra8_ipc_unit_ipc0 = 0U , k_ra8_ipc_unit_ipc1 = 1U }
	Logical IPC unit identifiers (IPC0 vs IPC1). More...
enum	ra8_ipc_core_id_t : uint8_t { k_ra8_ipc_core_cpu0 = 0U , k_ra8_ipc_core_cpu1 = 1U }
	Logical CPU core identifiers used by attribution helpers. More...
enum	ra8_ipc_sta_mask_t : uint32_t { k_ra8_ipc_sta_mask_irq0 = 0x00000001U , k_ra8_ipc_sta_mask_irq1 = 0x00000002U , k_ra8_ipc_sta_mask_irq2 = 0x00000004U , k_ra8_ipc_sta_mask_irq3 = 0x00000008U , k_ra8_ipc_sta_mask_irq4 = 0x00000010U , k_ra8_ipc_sta_mask_irq5 = 0x00000020U , k_ra8_ipc_sta_mask_irq6 = 0x00000040U , k_ra8_ipc_sta_mask_irq7 = 0x00000080U , k_ra8_ipc_sta_mask_irq_all = 0x000000FFU , k_ra8_ipc_sta_mask_rdy = 0x00010000U , k_ra8_ipc_sta_mask_full = 0x00020000U , k_ra8_ipc_sta_mask_rerr = 0x01000000U , k_ra8_ipc_sta_mask_ferr = 0x02000000U , k_ra8_ipc_sta_mask_event = 0x030000FFU , k_ra8_ipc_sta_mask_err_any = 0x03000000U }
	Bit masks for the IPCnSTAm "Status" registers. More...
enum	ra8_ipc_clr_mask_t : uint32_t { k_ra8_ipc_clr_mask_clr0 = 0x00000001U , k_ra8_ipc_clr_mask_clr1 = 0x00000002U , k_ra8_ipc_clr_mask_clr2 = 0x00000004U , k_ra8_ipc_clr_mask_clr3 = 0x00000008U , k_ra8_ipc_clr_mask_clr4 = 0x00000010U , k_ra8_ipc_clr_mask_clr5 = 0x00000020U , k_ra8_ipc_clr_mask_clr6 = 0x00000040U , k_ra8_ipc_clr_mask_clr7 = 0x00000080U , k_ra8_ipc_clr_mask_irq_all = 0x000000FFU , k_ra8_ipc_clr_mask_rst = 0x00010000U , k_ra8_ipc_clr_mask_rclr = 0x01000000U , k_ra8_ipc_clr_mask_fclr = 0x02000000U , k_ra8_ipc_clr_mask_all = 0x030100FFU }
	Bit masks for the IPCnCLRm "Clear" registers. More...
enum	ra8_ipc_iset_mask_t : uint32_t { k_ra8_ipc_iset_mask_set0 = 0x00000001U , k_ra8_ipc_iset_mask_set1 = 0x00000002U , k_ra8_ipc_iset_mask_set2 = 0x00000004U , k_ra8_ipc_iset_mask_set3 = 0x00000008U , k_ra8_ipc_iset_mask_set4 = 0x00000010U , k_ra8_ipc_iset_mask_set5 = 0x00000020U , k_ra8_ipc_iset_mask_set6 = 0x00000040U , k_ra8_ipc_iset_mask_set7 = 0x00000080U , k_ra8_ipc_iset_mask_all = 0x000000FFU }
	Bit masks for the IPCnISETm "IRQ Request Set" registers. More...
enum	ra8_ipc_nmi_mask_t : uint32_t { k_ra8_ipc_nmi_mask_bit = 0x00000001U }
	Bit masks for the IPC NMI status / set / clear registers. More...
enum	ra8_ipc_sem_mask_t : uint32_t { k_ra8_ipc_sem_mask_lock = 0x00000001U }
	Bit masks for the IPCSEMn semaphore register. More...
enum	ra8_ipcsar_mask_t : uint32_t { k_ra8_ipcsar_mask_saipcsem0 = 0x00000001U , k_ra8_ipcsar_mask_saipcsem1 = 0x00000002U , k_ra8_ipcsar_mask_saipcnmi0 = 0x00000100U , k_ra8_ipcsar_mask_saipcnmi1 = 0x00000200U , k_ra8_ipcsar_mask_saipcir0 = 0x00010000U , k_ra8_ipcsar_mask_saipcir1 = 0x00020000U , k_ra8_ipcsar_mask_saipcir2 = 0x00040000U , k_ra8_ipcsar_mask_saipcir3 = 0x00080000U }
	Bit masks for the IPCSAR Security Attribution Register. More...
enum	ra8_ipcpar_mask_t : uint32_t { k_ra8_ipcpar_mask_paipcsem0 = 0x00000001U , k_ra8_ipcpar_mask_paipcsem1 = 0x00000002U , k_ra8_ipcpar_mask_paipcnmi0 = 0x00000100U , k_ra8_ipcpar_mask_paipcnmi1 = 0x00000200U , k_ra8_ipcpar_mask_paipcir0 = 0x00010000U , k_ra8_ipcpar_mask_paipcir1 = 0x00020000U , k_ra8_ipcpar_mask_paipcir2 = 0x00040000U , k_ra8_ipcpar_mask_paipcir3 = 0x00080000U }
	Bit masks for the IPCPAR Privileged Attribution Register. More...
enum	ra8_ipc_attr_shift_t : uint8_t { k_ra8_ipc_attr_shift_ir_base = 16U , k_ra8_ipc_attr_shift_nmi_base = 8U }
	Bit positions of SAIPCIRn / PAIPCIRn within IPCSAR / IPCPAR. More...
enum	ra8_ipc_elc_event_t : uint16_t { k_ra8_ipc_elc_event_irq0 = 0x05BU , k_ra8_ipc_elc_event_irq1 = 0x05CU }
	ELC event numbers for the IPC maskable IRQs. More...
enum	ra8_ipc_sem_attr_group_t : uint8_t { k_ra8_ipc_sem_group_low = 0U , k_ra8_ipc_sem_group_high = 1U }
	IPCSEMn attribution-group selector (HUM Ch 3.3.1 p 227-228). More...

Functions
static volatile r_ipc_channel_regs_t *	ra8_ipc_channel (uint8_t channel)
	Get a pointer to one IPC FIFO channel register window.
static volatile r_ipc_nmi_regs_t *	ra8_ipc_nmi (uint8_t unit)
	Get a pointer to one IPC NMI unit register window.
static volatile uint32_t *	ra8_ipc_ipcsar (void)
	Get a pointer to the IPCSAR Security Attribution register.
static volatile uint32_t *	ra8_ipc_ipcpar (void)
	Get a pointer to the IPCPAR Privileged Attribution register.
static volatile uint32_t *	ra8_ipc_sem (uint8_t sem_id)
	Get a pointer to one IPCSEM hardware semaphore register.
static uint8_t	ra8_ipc_channel_to_unit (uint8_t channel)
	Map a logical channel id to its containing IPC unit.

Detailed Description

Inter-Processor Communication (IPC) register layout for the RA8D2.

The RA8D2 hosts two CPU cores (Cortex-M85 / "CPU0" and Cortex-M33 / "CPU1") connected by a single IPC peripheral block. The block is partitioned into two units:

IPC0 – traffic from CPU1 (M33) to CPU0 (M85), with one non-maskable interrupt path (IPC0NMI*) plus two independent 32-bit message FIFOs (channels IPC0_0 and IPC0_1). Each FIFO channel carries 8 maskable IRQ event lines, an RDY/FULL status pair, and FIFO read/write error flags.
IPC1 – mirror image, traffic from CPU0 (M85) to CPU1 (M33), with IPC1NMI*, IPC1_0 and IPC1_1.

In addition the block exposes 16 hardware semaphores (IPCSEM0..15) shared between the cores and a security/privilege attribution pair (IPCSAR / IPCPAR) hosted in the CPSCU register window.

Per-FIFO-channel registers (5 x 32-bit at +0x20 stride):

Offset	Name	Width	Purpose
0x00	STA	32	Status (IRQ/RDY/FULL/RERR/FERR)
0x04	ISET	32	IRQ request set (write-1-to-trigger)
0x08	TXD	32	FIFO transmit data (write-only)
0x0C	RXD	32	FIFO receive data (read-only)
0x10	CLR	32	Status / error / FIFO clear

Per-NMI-channel registers (3 x 32-bit at +0x10 stride):

Offset	Name	Width	Purpose
0x00	NMISTA	32	Non-maskable interrupt status (read-only)
0x04	NMISET	32	Write 1 to NMI bit -> raise NMI to peer
0x08	NMICLR	32	Write 1 to CLR bit -> clear NMISTA.NMI

Register offsets tracked against HUM Ch 3 "Inter-Processor Communication (IPC)" p 204-233.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_ipc_regs.h.

Enumeration Type Documentation

◆ ra8_ipc_addr_t

enum ra8_ipc_addr_t : uintptr_t

Memory-mapped base addresses for the IPC block and the CPSCU window that holds IPCSAR / IPCPAR.

Secure / non-secure aliases differ by bit 28 (0x40000000 vs 0x50000000). HAL code uses the secure alias since unit tests run with RA8_OFF_TARGET and the fake mmap covers the secure 0x4xxxxxxx peripheral window.

Enumerator
k_ra8_ipc_base_addr	IPC block base (Secure).
k_ra8_ipc_cpscu_addr	CPSCU base for IPCSAR/IPCPAR.
k_ra8_ipc_ipcsar_addr	IPC Security Attribution Reg.
k_ra8_ipc_ipcpar_addr	IPC Privileged Attribution Reg.

Definition at line 69 of file ra8_ipc_regs.h.

◆ ra8_ipc_attr_shift_t

enum ra8_ipc_attr_shift_t : uint8_t

Bit positions of SAIPCIRn / PAIPCIRn within IPCSAR / IPCPAR.

HUM Ch 3.2.1 "IPCSAR" p 205 places SAIPCIR0 at bit 16, SAIPCIR1 at bit 17, SAIPCIR2 at 18 and SAIPCIR3 at 19. IPCPAR mirrors these positions (HUM Ch 3.2.2 p 208) so the same shift works for both.

Enumerator
k_ra8_ipc_attr_shift_ir_base	SAIPCIR0 / PAIPCIR0 bit position.
k_ra8_ipc_attr_shift_nmi_base	SAIPCNMI0 / PAIPCNMI0 position.

Definition at line 309 of file ra8_ipc_regs.h.

◆ ra8_ipc_clr_mask_t

enum ra8_ipc_clr_mask_t : uint32_t

Bit masks for the IPCnCLRm "Clear" registers.

Verified against HUM Ch 3.2.14 "IPC0CLR0" p 216-217. CLR7..CLR0 in [7:0] cancel the corresponding IRQn status; bit [16] RST resets the message FIFO (also clears RDY + FULL); [24] RCLR clears RERR; [25] FCLR clears FERR.

Enumerator
k_ra8_ipc_clr_mask_clr0	CLR0 -> drop STA.IRQ0.
k_ra8_ipc_clr_mask_clr1	CLR1 -> drop STA.IRQ1.
k_ra8_ipc_clr_mask_clr2	CLR2 -> drop STA.IRQ2.
k_ra8_ipc_clr_mask_clr3	CLR3 -> drop STA.IRQ3.
k_ra8_ipc_clr_mask_clr4	CLR4 -> drop STA.IRQ4.
k_ra8_ipc_clr_mask_clr5	CLR5 -> drop STA.IRQ5.
k_ra8_ipc_clr_mask_clr6	CLR6 -> drop STA.IRQ6.
k_ra8_ipc_clr_mask_clr7	CLR7 -> drop STA.IRQ7.
k_ra8_ipc_clr_mask_irq_all	CLR7..CLR0 -> clear IRQn.
k_ra8_ipc_clr_mask_rst	RST: reset message FIFO.
k_ra8_ipc_clr_mask_rclr	RCLR: clear RERR.
k_ra8_ipc_clr_mask_fclr	FCLR: clear FERR.
k_ra8_ipc_clr_mask_all	Every clearable bit.

Definition at line 192 of file ra8_ipc_regs.h.

◆ ra8_ipc_core_id_t

enum ra8_ipc_core_id_t : uint8_t

Logical CPU core identifiers used by attribution helpers.

Matches the FSP convention (BSP_CFG_CPU_CORE 0 = Cortex-M85 / CPU0, 1 = Cortex-M33 / CPU1). Used by the channel-pair convention helper to decide which IPC unit a given core writes to and which it reads from.

Enumerator
k_ra8_ipc_core_cpu0	Cortex-M85 (primary core).
k_ra8_ipc_core_cpu1	Cortex-M33 (secondary core).

Definition at line 147 of file ra8_ipc_regs.h.

◆ ra8_ipc_elc_event_t

enum ra8_ipc_elc_event_t : uint16_t

ELC event numbers for the IPC maskable IRQs.

The RA8D2 collapses every IPCnIRQm line into the two ELC events documented in HUM Ch 18 "Event Link Controller (ELC)" event-list (verified against fsp/ra/fsp/src/bsp/mcu/ra8d2/bsp_elc.h): ELC_EVENT_IPC_IRQ0 = 0x05B carries IPC unit 0 channel 0 + 1, and ELC_EVENT_IPC_IRQ1 = 0x05C carries IPC unit 1. The driver casts these to ra8_elc_event_t when calling ra8_isr_register.

Enumerator
k_ra8_ipc_elc_event_irq0	Receiving-side IRQ for IPC0_*.
k_ra8_ipc_elc_event_irq1	Receiving-side IRQ for IPC1_*.

Definition at line 326 of file ra8_ipc_regs.h.

◆ ra8_ipc_iset_mask_t

enum ra8_ipc_iset_mask_t : uint32_t

Bit masks for the IPCnISETm "IRQ Request Set" registers.

Verified against HUM Ch 3.2.11 "IPC0ISET0" p 215. SET7..SET0 in [7:0] each raise the corresponding IRQn status bit which in turn triggers the maskable IPCnIRQm interrupt on the receiving core.

Enumerator
k_ra8_ipc_iset_mask_set0	SET0 -> IRQ0 request.
k_ra8_ipc_iset_mask_set1	SET1 -> IRQ1 request.
k_ra8_ipc_iset_mask_set2	SET2 -> IRQ2 request.
k_ra8_ipc_iset_mask_set3	SET3 -> IRQ3 request.
k_ra8_ipc_iset_mask_set4	SET4 -> IRQ4 request.
k_ra8_ipc_iset_mask_set5	SET5 -> IRQ5 request.
k_ra8_ipc_iset_mask_set6	SET6 -> IRQ6 request.
k_ra8_ipc_iset_mask_set7	SET7 -> IRQ7 request.
k_ra8_ipc_iset_mask_all	All eight SET bits.

Definition at line 217 of file ra8_ipc_regs.h.

◆ ra8_ipc_limits_t

enum ra8_ipc_limits_t : uint8_t

Counts and strides used by the driver / accessors.

HUM Ch 3.1 "Overview" p 204 fixes the FIFO depth at 4 stages and the per-channel maskable-IRQ-event count at 8. The stride values are derived from the register-address map on p 205.

Enumerator
k_ra8_ipc_sem_count	IPCSEM0..IPCSEM15.
k_ra8_ipc_nmi_unit_count	IPC0 + IPC1 NMI units.
k_ra8_ipc_channel_count	Total FIFO channels: 2 per unit x 2.
k_ra8_ipc_irq_event_count	8 IRQ event lines per channel.
k_ra8_ipc_fifo_depth	4 stages per FIFO (HUM 3.1).
k_ra8_ipc_channel_stride	Bytes between channel windows.
k_ra8_ipc_nmi_stride	Bytes between NMI unit windows.

Definition at line 111 of file ra8_ipc_regs.h.

◆ ra8_ipc_nmi_mask_t

enum ra8_ipc_nmi_mask_t : uint32_t

Bit masks for the IPC NMI status / set / clear registers.

HUM Ch 3.2.4 "IPC0NMISTA" p 210 + Ch 3.2.5 "IPC0NMISET" p 211 + Ch 3.2.6 "IPC0NMICLR" p 212 (mirrored on Ch 3.2.7..3.2.9 p 212- 213) document bit [0] as the only valid bit in NMISTA / NMISET / NMICLR.

Enumerator
k_ra8_ipc_nmi_mask_bit	Single-bit NMI request / status.

Definition at line 239 of file ra8_ipc_regs.h.

◆ ra8_ipc_offset_t

enum ra8_ipc_offset_t : uint16_t

In-block offsets relative to k_ra8_ipc_base_addr.

Verified against the IPC register address map figure on HUM Ch 3.2 "Register Descriptions" p 205. IPCSEM0..15 occupy 0x000.. 0x03C; the two NMI register triplets sit at 0x080 (IPC0) and 0x090 (IPC1); the four FIFO channel windows start at 0x0C0 (IPC0_0), 0x0E0 (IPC0_1), 0x100 (IPC1_0), 0x120 (IPC1_1).

Enumerator
k_ra8_ipc_offset_ipcsem0	First semaphore register.
k_ra8_ipc_offset_ipcsem15	Last semaphore register.
k_ra8_ipc_offset_ipc0nmista	IPC0 NMI status (CPU1 -> CPU0).
k_ra8_ipc_offset_ipc0nmiset	IPC0 NMI set.
k_ra8_ipc_offset_ipc0nmiclr	IPC0 NMI clear.
k_ra8_ipc_offset_ipc1nmista	IPC1 NMI status (CPU0 -> CPU1).
k_ra8_ipc_offset_ipc1nmiset	IPC1 NMI set.
k_ra8_ipc_offset_ipc1nmiclr	IPC1 NMI clear.
k_ra8_ipc_offset_ipc0_ch0	IPC0 channel 0 STA (FIFO00).
k_ra8_ipc_offset_ipc0_ch1	IPC0 channel 1 STA (FIFO01).
k_ra8_ipc_offset_ipc1_ch0	IPC1 channel 0 STA (FIFO10).
k_ra8_ipc_offset_ipc1_ch1	IPC1 channel 1 STA (FIFO11).

Definition at line 87 of file ra8_ipc_regs.h.

◆ ra8_ipc_sem_attr_group_t

enum ra8_ipc_sem_attr_group_t : uint8_t

IPCSEMn attribution-group selector (HUM Ch 3.3.1 p 227-228).

The semaphores are attributed in two groups of eight: IPCSEM0..7 share SAIPCSEM0/PAIPCSEM0 and IPCSEM8..15 share SAIPCSEM1/PAIPCSEM1 (HUM Ch 3.3.1 "Semaphore" p 228 Figure 3.2). The driver uses this enum so the security/privilege accessors can address either group without callers tracking which IPCSEM index lives where.

Enumerator
k_ra8_ipc_sem_group_low	IPCSEM0..IPCSEM7 attribution group.
k_ra8_ipc_sem_group_high	IPCSEM8..IPCSEM15 attribution group.

Definition at line 342 of file ra8_ipc_regs.h.

◆ ra8_ipc_sem_mask_t

enum ra8_ipc_sem_mask_t : uint32_t

Bit masks for the IPCSEMn semaphore register.

HUM Ch 3.2.3 "IPCSEMn" p 210 documents bit [0] LOCK as the only valid bit. Reading the register through a 32-bit access sets LOCK (test-and-set semantics): the read returns 0 if the acquisition succeeded, 1 if another core had already taken it. Writing 1 to LOCK releases the resource. Halfword and byte reads that do not include bit 0 do not trigger the set, which is why this driver only ever issues 32-bit accessors.

Enumerator
k_ra8_ipc_sem_mask_lock	LOCK bit (read-to-acquire).

Definition at line 256 of file ra8_ipc_regs.h.

◆ ra8_ipc_sta_mask_t

enum ra8_ipc_sta_mask_t : uint32_t

Bit masks for the IPCnSTAm "Status" registers.

Verified against HUM Ch 3.2.10 "IPC0STA0" p 214 (and the identical IPC0STA1 / IPC1STA0 / IPC1STA1 on pages 217, 220, 223). Bits [7:0] are the eight maskable IRQ event status bits; [16] RDY indicates the receive FIFO is non-empty; [17] FULL indicates the FIFO is full; [24] RERR signals a read from an empty FIFO; [25] FERR signals a write to a full FIFO.

Enumerator
k_ra8_ipc_sta_mask_irq0	IRQ0 event.
k_ra8_ipc_sta_mask_irq1	IRQ1 event.
k_ra8_ipc_sta_mask_irq2	IRQ2 event.
k_ra8_ipc_sta_mask_irq3	IRQ3 event.
k_ra8_ipc_sta_mask_irq4	IRQ4 event.
k_ra8_ipc_sta_mask_irq5	IRQ5 event.
k_ra8_ipc_sta_mask_irq6	IRQ6 event.
k_ra8_ipc_sta_mask_irq7	IRQ7 event.
k_ra8_ipc_sta_mask_irq_all	IRQ7..IRQ0 event bits.
k_ra8_ipc_sta_mask_rdy	RDY: FIFO non-empty.
k_ra8_ipc_sta_mask_full	FULL: FIFO full.
k_ra8_ipc_sta_mask_rerr	RERR: read-while-empty.
k_ra8_ipc_sta_mask_ferr	FERR: write-while-full.
k_ra8_ipc_sta_mask_event	Any event the ISR cares about.
k_ra8_ipc_sta_mask_err_any	RERR \| FERR.

Definition at line 164 of file ra8_ipc_regs.h.

◆ ra8_ipc_unit_id_t

enum ra8_ipc_unit_id_t : uint8_t

Logical IPC unit identifiers (IPC0 vs IPC1).

The IPC block is split into two mirror-image units (HUM Ch 3.1 "Overview" p 204): IPC0 carries CPU1 -> CPU0 traffic (M33 to M85 direction), IPC1 carries CPU0 -> CPU1 (M85 to M33). Channel id 0/1 maps to IPC0_0/IPC0_1 (unit 0); channel id 2/3 maps to IPC1_0/IPC1_1 (unit 1).

Enumerator
k_ra8_ipc_unit_ipc0	CPU1 -> CPU0 (M33 sends, M85 receives).
k_ra8_ipc_unit_ipc1	CPU0 -> CPU1 (M85 sends, M33 receives).

Definition at line 132 of file ra8_ipc_regs.h.

◆ ra8_ipcpar_mask_t

enum ra8_ipcpar_mask_t : uint32_t

Bit masks for the IPCPAR Privileged Attribution Register.

HUM Ch 3.2.2 "IPCPAR" p 208-209. Each bit selects "Privileged" (0) vs "Unprivileged" (1) access to the matching IPCSAR target group.

Enumerator
k_ra8_ipcpar_mask_paipcsem0	IPCSEM0..7 priv attr.
k_ra8_ipcpar_mask_paipcsem1	IPCSEM8..15 priv attr.
k_ra8_ipcpar_mask_paipcnmi0	IPC0NMI* priv attr.
k_ra8_ipcpar_mask_paipcnmi1	IPC1NMI* priv attr.
k_ra8_ipcpar_mask_paipcir0	IPC0 channel 0 priv attr.
k_ra8_ipcpar_mask_paipcir1	IPC0 channel 1 priv attr.
k_ra8_ipcpar_mask_paipcir2	IPC1 channel 0 priv attr.
k_ra8_ipcpar_mask_paipcir3	IPC1 channel 1 priv attr.

Definition at line 289 of file ra8_ipc_regs.h.

◆ ra8_ipcsar_mask_t

enum ra8_ipcsar_mask_t : uint32_t

Bit masks for the IPCSAR Security Attribution Register.

Verified against HUM Ch 3.2.1 "IPCSAR" p 205-207. Bit 0/1 control the security of IPCSEM[0..7] and IPCSEM[8..15]; bits 8/9 control the NMI register pair for IPC0/IPC1; bits 16..19 control the four IPC channel register groups.

Enumerator
k_ra8_ipcsar_mask_saipcsem0	IPCSEM0..7 secure attr.
k_ra8_ipcsar_mask_saipcsem1	IPCSEM8..15 secure attr.
k_ra8_ipcsar_mask_saipcnmi0	IPC0NMI* secure attr.
k_ra8_ipcsar_mask_saipcnmi1	IPC1NMI* secure attr.
k_ra8_ipcsar_mask_saipcir0	IPC0 channel 0 secure attr.
k_ra8_ipcsar_mask_saipcir1	IPC0 channel 1 secure attr.
k_ra8_ipcsar_mask_saipcir2	IPC1 channel 0 secure attr.
k_ra8_ipcsar_mask_saipcir3	IPC1 channel 1 secure attr.

Definition at line 270 of file ra8_ipc_regs.h.

Function Documentation

◆ ra8_ipc_channel()

volatile r_ipc_channel_regs_t * ra8_ipc_channel ( uint8_t channel )

inlinestatic

Get a pointer to one IPC FIFO channel register window.

Parameters

[in]

channel

Logical channel id 0..3:

0 = IPC0 channel 0 (CPU1 -> CPU0, FIFO00) at +0x0C0
1 = IPC0 channel 1 (CPU1 -> CPU0, FIFO01) at +0x0E0
2 = IPC1 channel 0 (CPU0 -> CPU1, FIFO10) at +0x100
3 = IPC1 channel 1 (CPU0 -> CPU1, FIFO11) at +0x120

Returns: Volatile pointer to the channel block, or nullptr when channel >= k_ra8_ipc_channel_count.

Definition at line 394 of file ra8_ipc_regs.h.

References k_ra8_ipc_base_addr, k_ra8_ipc_channel_count, k_ra8_ipc_channel_stride, and k_ra8_ipc_offset_ipc0_ch0.

Referenced by internal_ra8_ipc_get_regs(), and ra8_ipc_dispatch().

◆ ra8_ipc_channel_to_unit()

uint8_t ra8_ipc_channel_to_unit ( uint8_t channel )

inlinestatic

Map a logical channel id to its containing IPC unit.

Parameters

[in] channel Channel id 0..3.

Returns: Unit id (0 for channels 0/1, 1 for channels 2/3), or k_ra8_ipc_nmi_unit_count when channel is out of range (used as a sentinel by callers).

See implementation.

Return values

k_ra8_ok Operation succeeded.

Precondition: Module state is consistent.; Module state is consistent.

Postcondition: Caller-visible state matches the documented contract.; Caller-visible state matches the documented contract.

Note: Not thread-safe unless documented otherwise.

Since: 0.1.0

Definition at line 486 of file ra8_ipc_regs.h.

References k_ra8_ipc_channel_count, and k_ra8_ipc_nmi_unit_count.

◆ ra8_ipc_ipcpar()

volatile uint32_t * ra8_ipc_ipcpar ( void )

inlinestatic

Get a pointer to the IPCPAR Privileged Attribution register.

Returns: Volatile pointer to the 32-bit IPCPAR.

Definition at line 444 of file ra8_ipc_regs.h.

References k_ra8_ipc_ipcpar_addr.

Referenced by ra8_ipc_get_attribution(), ra8_ipc_get_nmi_attribution(), and ra8_ipc_get_sem_attribution().

◆ ra8_ipc_ipcsar()

volatile uint32_t * ra8_ipc_ipcsar ( void )

inlinestatic

Get a pointer to the IPCSAR Security Attribution register.

Returns: Volatile pointer to the 32-bit IPCSAR.

Definition at line 433 of file ra8_ipc_regs.h.

References k_ra8_ipc_ipcsar_addr.

Referenced by ra8_ipc_get_attribution(), ra8_ipc_get_nmi_attribution(), and ra8_ipc_get_sem_attribution().

◆ ra8_ipc_nmi()

volatile r_ipc_nmi_regs_t * ra8_ipc_nmi ( uint8_t unit )

inlinestatic

Get a pointer to one IPC NMI unit register window.

Parameters

[in]

unit

NMI unit id 0..1:

0 = IPC0 NMI (CPU1 -> CPU0) at +0x080
1 = IPC1 NMI (CPU0 -> CPU1) at +0x090

Returns: Volatile pointer to the NMI block, or nullptr when unit >= k_ra8_ipc_nmi_unit_count.

Definition at line 416 of file ra8_ipc_regs.h.

References k_ra8_ipc_base_addr, k_ra8_ipc_nmi_stride, k_ra8_ipc_nmi_unit_count, and k_ra8_ipc_offset_ipc0nmista.

Referenced by internal_ra8_ipc_get_nmi().

◆ ra8_ipc_sem()

volatile uint32_t * ra8_ipc_sem ( uint8_t sem_id )

inlinestatic

Get a pointer to one IPCSEM hardware semaphore register.

Parameters

[in] sem_id Semaphore index 0..15.

Returns: Volatile pointer to the semaphore register, or nullptr when sem_id >= k_ra8_ipc_sem_count.

Definition at line 458 of file ra8_ipc_regs.h.

References k_ra8_ipc_base_addr, and k_ra8_ipc_sem_count.

Referenced by ra8_ipc_sem_is_locked(), ra8_ipc_sem_release(), ra8_ipc_sem_take_timeout(), and ra8_ipc_sem_try_take().

Data Structures

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

◆ ra8_ipc_addr_t

◆ ra8_ipc_attr_shift_t

◆ ra8_ipc_clr_mask_t

◆ ra8_ipc_core_id_t

◆ ra8_ipc_elc_event_t

◆ ra8_ipc_iset_mask_t

◆ ra8_ipc_limits_t

◆ ra8_ipc_nmi_mask_t

◆ ra8_ipc_offset_t

◆ ra8_ipc_sem_attr_group_t

◆ ra8_ipc_sem_mask_t

◆ ra8_ipc_sta_mask_t

◆ ra8_ipc_unit_id_t

◆ ra8_ipcpar_mask_t

◆ ra8_ipcsar_mask_t

Function Documentation

◆ ra8_ipc_channel()

◆ ra8_ipc_channel_to_unit()

◆ ra8_ipc_ipcpar()

◆ ra8_ipc_ipcsar()

◆ ra8_ipc_nmi()

◆ ra8_ipc_sem()