ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_ipc_channel_regs_t Struct Reference

Per-FIFO-channel register window (5 x 32-bit at +0x20 stride). More...

#include <ra8_ipc_regs.h>

Data Fields

volatile uint32_t STA
 +0x00 Status (RDY/FULL/RERR/FERR/IRQn).
volatile uint32_t ISET
 +0x04 IRQ request set (W).
volatile uint32_t TXD
 +0x08 FIFO transmit data (W).
volatile uint32_t RXD
 +0x0C FIFO receive data (R).
volatile uint32_t CLR
 +0x10 Status / error / FIFO clear (W).
volatile uint32_t _pad [3]
 +0x14..+0x1F padding to next channel.

Detailed Description

Per-FIFO-channel register window (5 x 32-bit at +0x20 stride).

Layout matches the IPC0_0 (IPC0STA0..IPC0CLR0) block at offset 0x0C0 documented in HUM Ch 3.2.10..3.2.14 p 214-216, and is reused with offset 0x20/0x40/0x60 for IPC0_1, IPC1_0, IPC1_1 (see the IPC register address map figure on HUM p 205).

Definition at line 357 of file ra8_ipc_regs.h.

Field Documentation

◆ _pad

volatile uint32_t r_ipc_channel_regs_t::_pad[3]

+0x14..+0x1F padding to next channel.

Definition at line 363 of file ra8_ipc_regs.h.

◆ CLR

volatile uint32_t r_ipc_channel_regs_t::CLR

◆ ISET

volatile uint32_t r_ipc_channel_regs_t::ISET

+0x04 IRQ request set (W).

Definition at line 359 of file ra8_ipc_regs.h.

Referenced by ra8_ipc_send_event().

◆ RXD

volatile uint32_t r_ipc_channel_regs_t::RXD

+0x0C FIFO receive data (R).

Definition at line 361 of file ra8_ipc_regs.h.

Referenced by ra8_ipc_dispatch(), ra8_ipc_recv_burst(), ra8_ipc_recv_message(), and ra8_ipc_recv_message_retry().

◆ STA

◆ TXD

volatile uint32_t r_ipc_channel_regs_t::TXD

+0x08 FIFO transmit data (W).

Definition at line 360 of file ra8_ipc_regs.h.

Referenced by ra8_ipc_send_burst(), ra8_ipc_send_message(), and ra8_ipc_send_message_retry().


The documentation for this struct was generated from the following file: