ra8_ipc_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_ipc_base_addr   = 0x40020000UL, 
  k_ra8_ipc_cpscu_addr  = 0x40008000UL, 
  k_ra8_ipc_ipcsar_addr = 0x40008610UL, 
  k_ra8_ipc_ipcpar_addr = 0x40008614UL, 
} ra8_ipc_addr_t;

typedef enum : uint16_t {
  k_ra8_ipc_offset_ipcsem0    = 0x000U, 
  k_ra8_ipc_offset_ipcsem15   = 0x03CU, 
  k_ra8_ipc_offset_ipc0nmista = 0x080U, 
  k_ra8_ipc_offset_ipc0nmiset = 0x084U, 
  k_ra8_ipc_offset_ipc0nmiclr = 0x088U, 
  k_ra8_ipc_offset_ipc1nmista = 0x090U, 
  k_ra8_ipc_offset_ipc1nmiset = 0x094U, 
  k_ra8_ipc_offset_ipc1nmiclr = 0x098U, 
  k_ra8_ipc_offset_ipc0_ch0   = 0x0C0U, 
  k_ra8_ipc_offset_ipc0_ch1   = 0x0E0U, 
  k_ra8_ipc_offset_ipc1_ch0   = 0x100U, 
  k_ra8_ipc_offset_ipc1_ch1   = 0x120U, 
} ra8_ipc_offset_t;

typedef enum : uint8_t {
  k_ra8_ipc_sem_count       = 16U,   
  k_ra8_ipc_nmi_unit_count  = 2U,    
  k_ra8_ipc_channel_count   = 4U,    
  k_ra8_ipc_irq_event_count = 8U,    
  k_ra8_ipc_fifo_depth      = 4U,    
  k_ra8_ipc_channel_stride  = 0x20U, 
  k_ra8_ipc_nmi_stride      = 0x10U, 
} ra8_ipc_limits_t;

typedef enum : uint8_t {
  k_ra8_ipc_unit_ipc0 = 0U, 
  k_ra8_ipc_unit_ipc1 = 1U, 
} ra8_ipc_unit_id_t;

typedef enum : uint8_t {
  k_ra8_ipc_core_cpu0 = 0U, 
  k_ra8_ipc_core_cpu1 = 1U, 
} ra8_ipc_core_id_t;

typedef enum : uint32_t {
  k_ra8_ipc_sta_mask_irq0    = 0x00000001U, 
  k_ra8_ipc_sta_mask_irq1    = 0x00000002U, 
  k_ra8_ipc_sta_mask_irq2    = 0x00000004U, 
  k_ra8_ipc_sta_mask_irq3    = 0x00000008U, 
  k_ra8_ipc_sta_mask_irq4    = 0x00000010U, 
  k_ra8_ipc_sta_mask_irq5    = 0x00000020U, 
  k_ra8_ipc_sta_mask_irq6    = 0x00000040U, 
  k_ra8_ipc_sta_mask_irq7    = 0x00000080U, 
  k_ra8_ipc_sta_mask_irq_all = 0x000000FFU, 
  k_ra8_ipc_sta_mask_rdy     = 0x00010000U, 
  k_ra8_ipc_sta_mask_full    = 0x00020000U, 
  k_ra8_ipc_sta_mask_rerr    = 0x01000000U, 
  k_ra8_ipc_sta_mask_ferr    = 0x02000000U, 
  k_ra8_ipc_sta_mask_event   = 0x030000FFU, 
  k_ra8_ipc_sta_mask_err_any = 0x03000000U, 
} ra8_ipc_sta_mask_t;

typedef enum : uint32_t {
  k_ra8_ipc_clr_mask_clr0    = 0x00000001U, 
  k_ra8_ipc_clr_mask_clr1    = 0x00000002U, 
  k_ra8_ipc_clr_mask_clr2    = 0x00000004U, 
  k_ra8_ipc_clr_mask_clr3    = 0x00000008U, 
  k_ra8_ipc_clr_mask_clr4    = 0x00000010U, 
  k_ra8_ipc_clr_mask_clr5    = 0x00000020U, 
  k_ra8_ipc_clr_mask_clr6    = 0x00000040U, 
  k_ra8_ipc_clr_mask_clr7    = 0x00000080U, 
  k_ra8_ipc_clr_mask_irq_all = 0x000000FFU, 
  k_ra8_ipc_clr_mask_rst     = 0x00010000U, 
  k_ra8_ipc_clr_mask_rclr    = 0x01000000U, 
  k_ra8_ipc_clr_mask_fclr    = 0x02000000U, 
  k_ra8_ipc_clr_mask_all     = 0x030100FFU, 
} ra8_ipc_clr_mask_t;

typedef enum : uint32_t {
  k_ra8_ipc_iset_mask_set0 = 0x00000001U, 
  k_ra8_ipc_iset_mask_set1 = 0x00000002U, 
  k_ra8_ipc_iset_mask_set2 = 0x00000004U, 
  k_ra8_ipc_iset_mask_set3 = 0x00000008U, 
  k_ra8_ipc_iset_mask_set4 = 0x00000010U, 
  k_ra8_ipc_iset_mask_set5 = 0x00000020U, 
  k_ra8_ipc_iset_mask_set6 = 0x00000040U, 
  k_ra8_ipc_iset_mask_set7 = 0x00000080U, 
  k_ra8_ipc_iset_mask_all  = 0x000000FFU, 
} ra8_ipc_iset_mask_t;

typedef enum : uint32_t {
  k_ra8_ipc_nmi_mask_bit = 0x00000001U, 
} ra8_ipc_nmi_mask_t;

typedef enum : uint32_t {
  k_ra8_ipc_sem_mask_lock = 0x00000001U, 
} ra8_ipc_sem_mask_t;

typedef enum : uint32_t {
  k_ra8_ipcsar_mask_saipcsem0 = 0x00000001U, 
  k_ra8_ipcsar_mask_saipcsem1 = 0x00000002U, 
  k_ra8_ipcsar_mask_saipcnmi0 = 0x00000100U, 
  k_ra8_ipcsar_mask_saipcnmi1 = 0x00000200U, 
  k_ra8_ipcsar_mask_saipcir0  = 0x00010000U, 
  k_ra8_ipcsar_mask_saipcir1  = 0x00020000U, 
  k_ra8_ipcsar_mask_saipcir2  = 0x00040000U, 
  k_ra8_ipcsar_mask_saipcir3  = 0x00080000U, 
} ra8_ipcsar_mask_t;

typedef enum : uint32_t {
  k_ra8_ipcpar_mask_paipcsem0 = 0x00000001U, 
  k_ra8_ipcpar_mask_paipcsem1 = 0x00000002U, 
  k_ra8_ipcpar_mask_paipcnmi0 = 0x00000100U, 
  k_ra8_ipcpar_mask_paipcnmi1 = 0x00000200U, 
  k_ra8_ipcpar_mask_paipcir0  = 0x00010000U, 
  k_ra8_ipcpar_mask_paipcir1  = 0x00020000U, 
  k_ra8_ipcpar_mask_paipcir2  = 0x00040000U, 
  k_ra8_ipcpar_mask_paipcir3  = 0x00080000U, 
} ra8_ipcpar_mask_t;

typedef enum : uint8_t {
  k_ra8_ipc_attr_shift_ir_base  = 16U, 
  k_ra8_ipc_attr_shift_nmi_base = 8U,  
} ra8_ipc_attr_shift_t;

typedef enum : uint16_t {
  k_ra8_ipc_elc_event_irq0 = 0x05BU, 
  k_ra8_ipc_elc_event_irq1 = 0x05CU, 
} ra8_ipc_elc_event_t;

typedef enum : uint8_t {
  k_ra8_ipc_sem_group_low  = 0U, 
  k_ra8_ipc_sem_group_high = 1U, 
} ra8_ipc_sem_attr_group_t;

typedef struct {
  volatile uint32_t STA;     
  volatile uint32_t ISET;    
  volatile uint32_t TXD;     
  volatile uint32_t RXD;     
  volatile uint32_t CLR;     
  volatile uint32_t _pad[3]; 
} r_ipc_channel_regs_t;

typedef struct {
  volatile uint32_t NMISTA; 
  volatile uint32_t NMISET; 
  volatile uint32_t NMICLR; 
  volatile uint32_t _pad;   
} r_ipc_nmi_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_ipc_channel_regs_t* ra8_ipc_channel(uint8_t channel)
{
  if ((uint16_t)channel >= (uint16_t)k_ra8_ipc_channel_count) {
    return nullptr;
  }
  /* HUM Ch 3.2 "Register Descriptions" p 205 -- channel 0 starts at
   * +0x0C0 with a 0x20 stride between consecutive channels. */
  const uintptr_t base = k_ra8_ipc_base_addr + (uintptr_t)k_ra8_ipc_offset_ipc0_ch0 +
                         ((uintptr_t)channel * (uintptr_t)k_ra8_ipc_channel_stride);
  return (volatile r_ipc_channel_regs_t*)base;
}

RA8_HW_REGISTER_ACCESS
static inline volatile r_ipc_nmi_regs_t* ra8_ipc_nmi(uint8_t unit)
{
  if ((uint16_t)unit >= (uint16_t)k_ra8_ipc_nmi_unit_count) {
    return nullptr;
  }
  /* HUM Ch 3.2 "Register Descriptions" p 205 -- IPC0NMI at +0x080,
   * IPC1NMI at +0x090 (0x10 stride). */
  const uintptr_t base = k_ra8_ipc_base_addr + (uintptr_t)k_ra8_ipc_offset_ipc0nmista +
                         ((uintptr_t)unit * (uintptr_t)k_ra8_ipc_nmi_stride);
  return (volatile r_ipc_nmi_regs_t*)base;
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_ipc_ipcsar(void)
{
  /* HUM Ch 3.2.1 "IPCSAR" p 205 */
  return (volatile uint32_t*)k_ra8_ipc_ipcsar_addr;
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_ipc_ipcpar(void)
{
  /* HUM Ch 3.2.2 "IPCPAR" p 208 */
  return (volatile uint32_t*)k_ra8_ipc_ipcpar_addr;
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_ipc_sem(uint8_t sem_id)
{
  if ((uint16_t)sem_id >= (uint16_t)k_ra8_ipc_sem_count) {
    return nullptr;
  }
  /* HUM Ch 3.2.3 "IPCSEMn" p 210 -- IPCSEM0 at +0x000, each
   * semaphore is a 32-bit word so the stride is 4 bytes. */
  const uintptr_t base = k_ra8_ipc_base_addr + ((uintptr_t)sem_id * sizeof(uint32_t));
  return (volatile uint32_t*)base;
}

static inline uint8_t ra8_ipc_channel_to_unit(uint8_t channel)
{
  if ((uint16_t)channel >= (uint16_t)k_ra8_ipc_channel_count) {
    return k_ra8_ipc_nmi_unit_count;
  }
  /* HUM Ch 3.1 "Overview" p 204 -- channels 0/1 belong to IPC0,
   * channels 2/3 belong to IPC1. */
  return (uint8_t)(channel >> 1U);
}
 
#ifdef __cplusplus
}
#endif