53typedef enum : uint32_t {
64typedef enum : uint8_t {
95 __asm__
volatile(
"wfi");
111 uint32_t cpuclk0_hz = 0U;
173 uint32_t pclka_hz = 0U;
183 .pclka_hz = pclka_hz,
void main(void)
Secure fallback main entry point.
static void i3c_demo_panic_halt(void)
Park forever after a fatal init failure.
i3c_demo_byte_t
Probe address on the I3C ch0 bus.
@ k_i3c_demo_probe_addr
I3C demo probe address.
i3c_demo_const_t
App-wide tunables.
@ k_i3c_demo_period_ms
I3C demo period ms.
@ k_i3c_demo_iic_channel
I3C demo iic channel.
@ k_i3c_demo_baud
I3C demo baud.
@ k_i3c_demo_bus_hz
I3C demo bus Hz.
static void i3c_demo_clocks_or_halt(uint32_t *out_pclka_hz)
Bring CGC + SysTick + MSTP up; return PCLKA via out_pclka_hz.
static const uint8_t k_i3c_demo_msg_err[]
static const ra8_port_pin_t k_i3c_demo_pin_scl
Pinout for I3C channel 0 (P400 SCL0 / P401 SDA0 on EK-RA8D2), routed to the J27 header (board UM sect...
static const uint8_t k_i3c_demo_msg_nack[]
static void i3c_demo_setup_or_halt(void)
Bring CGC + SysTick + console + IIC_B up.
static const ra8_port_pin_t k_i3c_demo_pin_sda
static const uint8_t k_i3c_demo_msg_ack[]
static void i3c_demo_pfs_or_halt(void)
Route IIC channel-0 SCL/SDA via PFS.
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led2
LED2, GREEN, P303 (jumper E26).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
@ k_ra8_board_i3c0_pin_scl
P400 SCL0.
@ k_ra8_board_i3c0_pin_sda
P401 SDA0.
ra8_err_t ra8_board_uart_console_write(const uint8_t *data, size_t len)
Polled blocking write to the J-Link OB VCOM console.
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
Configure SCI8 + PD02/PD03 as the debug-console UART.
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
@ k_ra8_clock_id_pclka
PCLKA.
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
PSEL codes for peripheral pin routing on the RA8D2.
@ k_ra8_psel_iic
00111b: IIC / I3C controller-peripheral.
I3C Bus Interface driver – unified native-I3C + I2C-compat modes.
@ k_ra8_i3c_mode_i2c
Legacy I2C-compatibility controller.
ra8_err_t ra8_i3c_scan(uint8_t channel, uint8_t addr, bool *out_acked)
Probe whether a 7-bit address acknowledges (I2C mode).
ra8_err_t ra8_i3c_init(uint8_t channel, const ra8_i3c_cfg_t *cfg)
Initialise an I3C channel in the configured mode.
NVIC + ICU IELSR allocator.
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Multi-function Pin Controller (MPC) facade.
ra8_err_t ra8_mpc_set_open_drain(ra8_port_t port, ra8_pin_t pin, bool enable)
Enable or disable N-channel open-drain on a pin.
Ref-counted Module Stop Control wrapper for the RA8D2.
ra8_err_t ra8_mstp_init(void)
Re-establish the ra8_mstp ref-count table from current hardware state.
ra8_port_pin_t
Packed (port << 8) | pin pin identifier.
@ k_ra8_port_4
RA8 port 4.
High-level GPIO helpers on top of the PORT + PFS register layer.
ra8_err_t ra8_pfs_route_peripheral(ra8_port_pin_t pin, ra8_psel_t psel, const char *owner)
Route a pin to a non-IRQ peripheral function via PFS.PSEL.
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Per-channel bring-up configuration for ra8_i3c_init.