ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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main.c
Go to the documentation of this file.
1
37
38#include <stdint.h>
39
40#include "ra8_board_ek_ra8d2.h"
41#include "ra8_boot_entry.h"
42#include "ra8_cgc.h"
43#include "ra8_err.h"
44#include "ra8_gpio_constants.h"
45#include "ra8_i3c.h"
46#include "ra8_isr.h"
47#include "ra8_mpc.h"
48#include "ra8_mstp.h"
49#include "ra8_port_utils.h"
50#include "ra8_time.h"
51
53typedef enum : uint32_t {
54 k_i3c_demo_baud = 115200U,
59
64typedef enum : uint8_t {
67
75
76/* Controller bring-up banners. Reaching this loop at all proves
77 * ra8_i3c_init configured + powered the I3C controller on real silicon
78 * (init failure panic-halts before the loop), so every banner leads with
79 * "i3c: ctrl init ok". The scan outcome is reported but not gated: on a
80 * bare EVM the ch0/J27 bus floats (no device, no pull-ups) so the
81 * transaction cannot complete -- attach a device to J27 to see ack=1. */
82static const uint8_t k_i3c_demo_msg_ack[] = "i3c: ctrl init ok | scan 0x43 ack=1\r\n";
83static const uint8_t k_i3c_demo_msg_nack[] = "i3c: ctrl init ok | scan 0x43 ack=0\r\n";
84static const uint8_t k_i3c_demo_msg_err[] = "i3c: ctrl init ok | bus idle on J27 (bare EVM)\r\n";
85
92static void i3c_demo_panic_halt(void)
93{
94 while (1) {
95 __asm__ volatile("wfi");
96 }
97}
98
109static void i3c_demo_clocks_or_halt(uint32_t* out_pclka_hz)
110{
111 uint32_t cpuclk0_hz = 0U;
112 if (ra8_cgc_init() != k_ra8_ok) {
114 }
117 }
118 if (ra8_cgc_get_clock_hz(k_ra8_clock_id_pclka, out_pclka_hz) != k_ra8_ok) {
120 }
121 if (ra8_mstp_init() != k_ra8_ok) {
123 }
124 if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
126 }
127}
128
137static void i3c_demo_pfs_or_halt(void)
138{
140 k_ra8_ok) {
142 }
144 k_ra8_ok) {
146 }
147
148 /* IIC_B requires N-channel open-drain on SCL/SDA so the on-board
149 * pullups can win bus arbitration; ra8_pfs_route_peripheral routes
150 * the IIC mux but leaves NCODR clear (push-pull). Mirrors the
151 * same NCODR write in
152 * ra8_board_ek_ra8d2.c::internal_io_expander_route_pins.
153 * HUM Ch 20.2.1 "PmnPFS Register" p 855 + HUM Ch 40 "IIC_B" p 2436 */
156 }
159 }
160}
161
171static void i3c_demo_setup_or_halt(void)
172{
173 uint32_t pclka_hz = 0U;
174 i3c_demo_clocks_or_halt(&pclka_hz);
176
179 }
180 const ra8_i3c_cfg_t iic_cfg = {
181 .mode = k_ra8_i3c_mode_i2c,
182 .bus_hz = k_i3c_demo_bus_hz,
183 .pclka_hz = pclka_hz,
184 };
185 if (ra8_i3c_init((uint8_t)k_i3c_demo_iic_channel, &iic_cfg) != k_ra8_ok) {
187 }
190 }
193 }
194}
195
207void main(void)
208{
211
212 while (1) {
213 bool acked = false;
214 const ra8_err_t err =
216 const uint8_t* msg = k_i3c_demo_msg_err;
217 uint32_t msg_len = (uint32_t)(sizeof(k_i3c_demo_msg_err) - 1U);
218 if (err == k_ra8_ok) {
219 if (acked) {
220 msg = k_i3c_demo_msg_ack;
221 msg_len = (uint32_t)(sizeof(k_i3c_demo_msg_ack) - 1U);
222 } else {
224 msg_len = (uint32_t)(sizeof(k_i3c_demo_msg_nack) - 1U);
225 }
226 }
227 if (ra8_board_uart_console_write(msg, (size_t)msg_len) != k_ra8_ok) {
228 break;
229 }
231 break;
232 }
234 }
235
237}
void main(void)
Secure fallback main entry point.
Definition main.c:37
static void i3c_demo_panic_halt(void)
Park forever after a fatal init failure.
Definition main.c:92
i3c_demo_byte_t
Probe address on the I3C ch0 bus.
Definition main.c:64
@ k_i3c_demo_probe_addr
I3C demo probe address.
Definition main.c:65
i3c_demo_const_t
App-wide tunables.
Definition main.c:53
@ k_i3c_demo_period_ms
I3C demo period ms.
Definition main.c:55
@ k_i3c_demo_iic_channel
I3C demo iic channel.
Definition main.c:57
@ k_i3c_demo_baud
I3C demo baud.
Definition main.c:54
@ k_i3c_demo_bus_hz
I3C demo bus Hz.
Definition main.c:56
static void i3c_demo_clocks_or_halt(uint32_t *out_pclka_hz)
Bring CGC + SysTick + MSTP up; return PCLKA via out_pclka_hz.
Definition main.c:109
static const uint8_t k_i3c_demo_msg_err[]
Definition main.c:84
static const ra8_port_pin_t k_i3c_demo_pin_scl
Pinout for I3C channel 0 (P400 SCL0 / P401 SDA0 on EK-RA8D2), routed to the J27 header (board UM sect...
Definition main.c:73
static const uint8_t k_i3c_demo_msg_nack[]
Definition main.c:83
static void i3c_demo_setup_or_halt(void)
Bring CGC + SysTick + console + IIC_B up.
Definition main.c:171
static const ra8_port_pin_t k_i3c_demo_pin_sda
Definition main.c:74
static const uint8_t k_i3c_demo_msg_ack[]
Definition main.c:82
static void i3c_demo_pfs_or_halt(void)
Route IIC channel-0 SCL/SDA via PFS.
Definition main.c:137
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_led_toggle(ra8_board_led_id_t led)
Toggle led's output state.
ra8_err_t ra8_board_led_init(ra8_board_led_id_t led)
Configure led as a digital output, initial level low (off).
@ k_ra8_board_led2
LED2, GREEN, P303 (jumper E26).
@ k_ra8_board_led1
LED1, BLUE, P600 (jumper E27).
@ k_ra8_board_i3c0_pin_scl
P400 SCL0.
@ k_ra8_board_i3c0_pin_sda
P401 SDA0.
ra8_err_t ra8_board_uart_console_write(const uint8_t *data, size_t len)
Polled blocking write to the J-Link OB VCOM console.
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
Configure SCI8 + PD02/PD03 as the debug-console UART.
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
Definition ra8_cgc.c:132
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
Definition ra8_cgc.h:70
@ k_ra8_clock_id_pclka
PCLKA.
Definition ra8_cgc.h:73
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Definition ra8_cgc.c:727
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
PSEL codes for peripheral pin routing on the RA8D2.
@ k_ra8_psel_iic
00111b: IIC / I3C controller-peripheral.
I3C Bus Interface driver – unified native-I3C + I2C-compat modes.
@ k_ra8_i3c_mode_i2c
Legacy I2C-compatibility controller.
Definition ra8_i3c.h:69
ra8_err_t ra8_i3c_scan(uint8_t channel, uint8_t addr, bool *out_acked)
Probe whether a 7-bit address acknowledges (I2C mode).
Definition ra8_i3c.c:729
ra8_err_t ra8_i3c_init(uint8_t channel, const ra8_i3c_cfg_t *cfg)
Initialise an I3C channel in the configured mode.
Definition ra8_i3c.c:311
NVIC + ICU IELSR allocator.
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Definition ra8_isr.c:439
Multi-function Pin Controller (MPC) facade.
ra8_err_t ra8_mpc_set_open_drain(ra8_port_t port, ra8_pin_t pin, bool enable)
Enable or disable N-channel open-drain on a pin.
Definition ra8_mpc.c:198
Ref-counted Module Stop Control wrapper for the RA8D2.
ra8_err_t ra8_mstp_init(void)
Re-establish the ra8_mstp ref-count table from current hardware state.
Definition ra8_mstp.c:291
ra8_port_pin_t
Packed (port << 8) | pin pin identifier.
@ k_ra8_port_4
RA8 port 4.
@ k_ra8_pin_1
RA8 pin 1.
@ k_ra8_pin_0
RA8 pin 0.
High-level GPIO helpers on top of the PORT + PFS register layer.
ra8_err_t ra8_pfs_route_peripheral(ra8_port_pin_t pin, ra8_psel_t psel, const char *owner)
Route a pin to a non-IRQ peripheral function via PFS.PSEL.
Definition gpio.c:238
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
Definition ra8_time.c:59
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Definition ra8_time.c:129
Per-channel bring-up configuration for ra8_i3c_init.
Definition ra8_i3c.h:90