main.c File Reference

I3C (ra8_i3c) controller bring-up self-test for the EK-RA8D2. More...

#include <stdint.h>
#include "ra8_board_ek_ra8d2.h"
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_i3c.h"
#include "ra8_isr.h"
#include "ra8_mpc.h"
#include "ra8_mstp.h"
#include "ra8_port_utils.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Go to the source code of this file.

Enumerations
enum	i3c_demo_const_t : uint32_t {   k_i3c_demo_baud = 115200U ,   k_i3c_demo_period_ms = 1000U ,   k_i3c_demo_bus_hz = 100000U ,   k_i3c_demo_iic_channel = 0U }
	App-wide tunables. More...
enum	i3c_demo_byte_t : uint8_t { k_i3c_demo_probe_addr = 0x43U }
	Probe address on the I3C ch0 bus. More...

Functions
static void	i3c_demo_panic_halt (void)
	Park forever after a fatal init failure.
static void	i3c_demo_clocks_or_halt (uint32_t *out_pclka_hz)
	Bring CGC + SysTick + MSTP up; return PCLKA via out_pclka_hz.
static void	i3c_demo_pfs_or_halt (void)
	Route IIC channel-0 SCL/SDA via PFS.
static void	i3c_demo_setup_or_halt (void)
	Bring CGC + SysTick + console + IIC_B up.
void	main (void)
	Application entry.

Variables
static const ra8_port_pin_t	k_i3c_demo_pin_scl = (ra8_port_pin_t)k_ra8_board_i3c0_pin_scl
	Pinout for I3C channel 0 (P400 SCL0 / P401 SDA0 on EK-RA8D2), routed to the J27 header (board UM section 5.4.2 Table 31 row J27-1/J27-2 p ~32).
static const ra8_port_pin_t	k_i3c_demo_pin_sda = (ra8_port_pin_t)k_ra8_board_i3c0_pin_sda
static const uint8_t	k_i3c_demo_msg_ack [] = "i3c: ctrl init ok | scan 0x43 ack=1\r\n"
static const uint8_t	k_i3c_demo_msg_nack [] = "i3c: ctrl init ok | scan 0x43 ack=0\r\n"
static const uint8_t	k_i3c_demo_msg_err [] = "i3c: ctrl init ok | bus idle on J27 (bare EVM)\r\n"

Detailed Description

I3C (ra8_i3c) controller bring-up self-test for the EK-RA8D2.

Tag

[Ring 6 / APP] {World: S}

Standalone EVM-tier app that exercises the ra8_i3c controller driver in I2C-compatibility mode (libs/ra8_hal/inc/ra8_i3c.h) on channel 0. The I3C peripheral's ch0 bus (P400 SCL0 / P401 SDA0) routes to the J27 header (board UM section 5.4.2 Table 31), which has no guaranteed on-board device – U15 lives on RIIC ch1 (see i2c_loopback and #46). So this is a controller self-test: it proves ra8_i3c powers up and clocks a real START / address / STOP, not a data round-trip. The flow:

1. ra8_cgc_init – bring CPUCLK0 / PCLKA up.
2. ra8_board_uart_console_init for the SCI8 J-Link console plus ra8_pfs_route_peripheral for SCL0/SDA0 (P400/P401) with NCODR open-drain on the IIC pins.
3. ra8_i3c_init(0, ...) at 100 kHz Sm (I2C-compatibility mode).
4. ra8_i3c_scan against 0x43 in a loop. A k_ra8_ok return means the controller completed the transaction (the bus clocked); ack=0 is expected on a bare EVM (no device on J27), ack=1 only if a device is attached. A HAL error means the controller did not clock (bus wedged / mis-configured).
5. LED1 toggles each scan; SCI8 prints "i3c: ctrl up ..." on a completed scan or "i3c: scan ERROR" on a HAL error; LED2 latches ON on error.

Hardware: bare EK-RA8D2 v1. Attach an I2C device to J27 to see ack=1.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file main.c.

Enumeration Type Documentation

i3c_demo_byte_t

enum i3c_demo_byte_t : uint8_t

Probe address on the I3C ch0 bus.

0x43 is U15's address on RIIC ch1; reused here purely as a scan target. There is no device at 0x43 on the I3C bus, so a bare EVM NACKs (ack=0) – a completed scan (k_ra8_ok) still proves the controller clocks.

Enumerator
k_i3c_demo_probe_addr	I3C demo probe address.

Definition at line 64 of file main.c.

i3c_demo_const_t

enum i3c_demo_const_t : uint32_t

App-wide tunables.

Enumerator
k_i3c_demo_baud	I3C demo baud.
k_i3c_demo_period_ms	I3C demo period ms.
k_i3c_demo_bus_hz	I3C demo bus Hz.
k_i3c_demo_iic_channel	I3C demo iic channel.

Definition at line 53 of file main.c.

Function Documentation

i3c_demo_clocks_or_halt()

void i3c_demo_clocks_or_halt ( uint32_t * out_pclka_hz )

static

Bring CGC + SysTick + MSTP up; return PCLKA via out_pclka_hz.

Parameters

[out]

out_pclka_hz

Receives the live PCLKA frequency.

Precondition

IRQs masked or single-threaded init context.

Postcondition

On success *out_pclka_hz is non-zero and CGC is live.

Since

0.1.0

Definition at line 109 of file main.c.

References i3c_demo_panic_halt(), k_ra8_clock_id_cpuclk0, k_ra8_clock_id_pclka, k_ra8_ok, ra8_cgc_get_clock_hz(), ra8_cgc_init(), ra8_mstp_init(), and ra8_time_init().

Referenced by i3c_demo_setup_or_halt().

i3c_demo_panic_halt()

void i3c_demo_panic_halt ( void )

static

Park forever after a fatal init failure.

Precondition

Called only after a fatal error in boot.

Postcondition

CPU is parked; only a debugger or external reset wakes it.

Since

0.1.0

Definition at line 92 of file main.c.

Referenced by i3c_demo_clocks_or_halt(), i3c_demo_pfs_or_halt(), i3c_demo_setup_or_halt(), and main().

i3c_demo_pfs_or_halt()

void i3c_demo_pfs_or_halt ( void )

static

Route IIC channel-0 SCL/SDA via PFS.

Precondition

ra8_mstp_init already ran so PFS writes land.

Postcondition

Both IIC pins are in their peripheral PSEL on success.

Since

0.1.0

Definition at line 137 of file main.c.

References i3c_demo_panic_halt(), k_i3c_demo_pin_scl, k_i3c_demo_pin_sda, k_ra8_ok, k_ra8_pin_0, k_ra8_pin_1, k_ra8_port_4, k_ra8_psel_iic, ra8_mpc_set_open_drain(), and ra8_pfs_route_peripheral().

Referenced by i3c_demo_setup_or_halt().

i3c_demo_setup_or_halt()

void i3c_demo_setup_or_halt ( void )

static

Bring CGC + SysTick + console + IIC_B up.

Panic-halts on any fail.

Pulls PCLKA via ra8_cgc_get_clock_hz so the IIC_B BRR computation tracks whatever clock tree the CGC driver is set to.

Since

0.1.0

Definition at line 171 of file main.c.

References i3c_demo_clocks_or_halt(), i3c_demo_panic_halt(), i3c_demo_pfs_or_halt(), k_i3c_demo_baud, k_i3c_demo_bus_hz, k_i3c_demo_iic_channel, k_ra8_board_led1, k_ra8_board_led2, k_ra8_i3c_mode_i2c, k_ra8_ok, ra8_board_led_init(), ra8_board_uart_console_init(), and ra8_i3c_init().

Referenced by main().

main()

void main

(

void

)

Application entry.

The application entry point Reset_Handler hands control to.

Brings up CGC + IIC_B + console then probes.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the scan + blink loop forever.

On any HAL hard error LED2 latches ON and the loop exits.

Since

0.1.0

Definition at line 207 of file main.c.

References i3c_demo_panic_halt(), i3c_demo_setup_or_halt(), k_i3c_demo_iic_channel, k_i3c_demo_msg_ack, k_i3c_demo_msg_err, k_i3c_demo_msg_nack, k_i3c_demo_period_ms, k_i3c_demo_probe_addr, k_ra8_board_led1, k_ra8_ok, ra8_board_led_toggle(), ra8_board_uart_console_write(), ra8_delay_ms(), ra8_i3c_scan(), and ra8_isr_globals_enable().

Variable Documentation

k_i3c_demo_msg_ack

const uint8_t k_i3c_demo_msg_ack[] = "i3c: ctrl init ok | scan 0x43 ack=1\r\n"

static

Definition at line 82 of file main.c.

Referenced by main().

k_i3c_demo_msg_err

const uint8_t k_i3c_demo_msg_err[] = "i3c: ctrl init ok | bus idle on J27 (bare EVM)\r\n"

static

Definition at line 84 of file main.c.

Referenced by main().

k_i3c_demo_msg_nack

const uint8_t k_i3c_demo_msg_nack[] = "i3c: ctrl init ok | scan 0x43 ack=0\r\n"

static

Definition at line 83 of file main.c.

Referenced by main().

k_i3c_demo_pin_scl

const ra8_port_pin_t k_i3c_demo_pin_scl = (ra8_port_pin_t)k_ra8_board_i3c0_pin_scl

static

Pinout for I3C channel 0 (P400 SCL0 / P401 SDA0 on EK-RA8D2), routed to the J27 header (board UM section 5.4.2 Table 31 row J27-1/J27-2 p ~32).

No on-board device sits here – this is the I3C peripheral's I2C-compat bus, exercised as a controller self-test.

Definition at line 73 of file main.c.

Referenced by i3c_demo_pfs_or_halt().

k_i3c_demo_pin_sda

const ra8_port_pin_t k_i3c_demo_pin_sda = (ra8_port_pin_t)k_ra8_board_i3c0_pin_sda

static

Definition at line 74 of file main.c.

Referenced by i3c_demo_pfs_or_halt().