ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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main.c
Go to the documentation of this file.
1
50
51#include <stdint.h>
52
53#include "ra8_attributes.h"
54#include "ra8_board_ek_ra8d2.h"
55#include "ra8_boot_entry.h"
56#include "ra8_cgc.h"
57#include "ra8_elc_regs.h"
58#include "ra8_err.h"
59#include "ra8_isr.h"
60#include "ra8_lpm.h"
61#include "ra8_lpm_regs.h"
62#include "ra8_time.h"
63#include "ra8_ulpt.h"
64
66typedef enum : uint32_t {
67 k_lus_baud = 115200U,
68 /* ULPTLCLK = LOCO / 1 = 32.768 kHz; 0x4000 (16384) ticks ~= 0.5 s. A
69 * sub-second period keeps the bench wake banner prompt without
70 * spinning the console. */
72 /* Bounded spin (NASA P10 Rule 2) waiting for ULPTCR.TCSTF to confirm
73 * the count actually started before we drop into standby. */
76
78typedef enum : uint8_t {
81
89static const uint8_t s_lus_boot_msg[] = "lpm_ulpt: boot\r\n";
90
98static const uint8_t s_lus_wake_msg[] = "lpm_ulpt: wake\r\n";
99
114volatile uint32_t g_lpm_ulpt_wake_count = 0U;
115
128{
129 while (1) {
130 __asm__ volatile("wfi");
131 }
132}
133
157{
158 (void)ctx;
160}
161
187[[nodiscard]] RA8_INTERNAL static ra8_err_t internal_lus_wait_count_started(uint8_t channel)
188{
189 const uint8_t tcstf_mask = (uint8_t)(1U << (uint8_t)k_ra8_ulpt_bit_tcstf);
190 for (uint32_t i = 0U; i < (uint32_t)k_lus_tcstf_poll_limit; ++i) {
191 uint8_t status = 0U;
192 ra8_err_t err = ra8_ulpt_get_status(channel, &status);
193 if (err != k_ra8_ok) {
194 return err;
195 }
196 if ((status & tcstf_mask) != 0U) {
197 return k_ra8_ok;
198 }
199 }
201}
202
223{
224 uint32_t cpuclk0_hz = 0U;
225 if (ra8_cgc_init() != k_ra8_ok) {
227 }
230 }
231 if (ra8_time_init(cpuclk0_hz) != k_ra8_ok) {
233 }
236 }
237 if (ra8_ulpt_init() != k_ra8_ok) {
239 }
240 const ra8_lpm_config_t lpm_cfg = {
241 .io_port_keep = false,
242 .opa_bus_keep = true,
243 .sscr_fast_return = false,
244 .dcdc_softstart = k_ra8_lpm_dcssmode_128us,
245 .sscr_low_power = k_ra8_lpm_ss2lp_default,
246 };
247 if (ra8_lpm_init(&lpm_cfg) != k_ra8_ok) {
249 }
250 /* Keep LOCO running (LCSTP = 0) so ULPTLCLK survives Software Standby:
251 * HUM Table 11.3 footnote *2 (p 433) -- with IWDT unused and
252 * LOCOCR.LCSTP = 0, LOCO is not stopped in Software Standby. */
255 }
256}
257
286{
287 ra8_err_t err = ra8_isr_init();
288 if (err != k_ra8_ok) {
289 return err;
290 }
293 nullptr,
294 (uint8_t)k_ra8_isr_prio_default,
295 nullptr);
296 if (err != k_ra8_ok) {
297 return err;
298 }
300}
301
302void main(void)
303{
305
308 }
310
311 (void)ra8_board_uart_console_write(s_lus_boot_msg, (size_t)(sizeof(s_lus_boot_msg) - 1U));
312
313 while (1) {
314 /* Re-arm the ULPT countdown, then drop into Software Standby until
315 * the underflow cancels it. ra8_ulpt_stop clears ULPTCR.TUNF so the
316 * next cycle starts clean. */
317 if (ra8_ulpt_start((uint8_t)k_lus_channel, (uint32_t)k_lus_period_ticks) != k_ra8_ok) {
318 break;
319 }
321 break;
322 }
324 break;
325 }
326 if (ra8_ulpt_stop((uint8_t)k_lus_channel) != k_ra8_ok) {
327 break;
328 }
329 if (ra8_board_uart_console_write(s_lus_wake_msg, (size_t)(sizeof(s_lus_wake_msg) - 1U)) !=
330 k_ra8_ok) {
331 break;
332 }
333 }
335}
void main(void)
Secure fallback main entry point.
Definition main.c:37
lus_const_t
Demo tunables.
Definition main.c:66
@ k_lus_period_ticks
Lus period ticks.
Definition main.c:71
@ k_lus_tcstf_poll_limit
Lus tcstf poll limit.
Definition main.c:74
@ k_lus_baud
SCI8 console baud rate.
Definition main.c:67
static const uint8_t s_lus_boot_msg[]
Boot banner emitted once before the first standby entry.
Definition main.c:89
static void internal_lus_panic_halt(void)
Park the processor after an unrecoverable setup or arm failure.
Definition main.c:127
static ra8_err_t internal_lus_arm_wake(void)
Wire the ULPT0 underflow as a Software-Standby wake source.
Definition main.c:285
volatile uint32_t g_lpm_ulpt_wake_count
Liveness counter – bumped in the ULPT0 underflow ISR.
Definition main.c:114
static ra8_err_t internal_lus_wait_count_started(uint8_t channel)
Spin until the ULPT count operation has actually started.
Definition main.c:187
static void internal_lus_ulpt_isr(void *ctx)
ULPT0 underflow interrupt service routine.
Definition main.c:156
static const uint8_t s_lus_wake_msg[]
Wake banner and per-underflow HIL gate string.
Definition main.c:98
lus_chan_t
ULPT channel selector.
Definition main.c:78
@ k_lus_channel
ULPT0 (its underflow is the wake source).
Definition main.c:79
static void internal_lus_setup_or_halt(void)
Bring CGC + SysTick + SCI8 + ULPT + LPM block up.
Definition main.c:222
Annotation-attribute framework macros for ra8-firmware.
#define RA8_INTERNAL
Marker that a function is intended to be static (file-local).
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
ra8_err_t ra8_board_uart_console_write(const uint8_t *data, size_t len)
Polled blocking write to the J-Link OB VCOM console.
ra8_err_t ra8_board_uart_console_init(uint32_t baud)
Configure SCI8 + PD02/PD03 as the debug-console UART.
Boot entry points shared between a vector table and its startup code.
High-level Clock Generation Circuit driver.
ra8_err_t ra8_cgc_get_clock_hz(ra8_clock_id_t id, uint32_t *out_hz)
Query the current frequency of a clock-tree domain.
Definition ra8_cgc.c:132
@ k_ra8_clock_id_cpuclk0
Cortex-M85 CPUCLK0.
Definition ra8_cgc.h:70
ra8_err_t ra8_cgc_init(void)
Configure the clock tree to a safe default.
Definition ra8_cgc.c:727
Event Link Controller (ELC) register layout for the Renesas RA8D2.
@ k_ra8_elc_event_ulpt0_ulpti
ULPT0 underflow (counter reaches 0).
Error Code Definitions for ra8-firmware.
@ k_ra8_err_hw_timeout
Hardware timed out waiting for a flag or handshake.
Definition ra8_err.h:304
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
NVIC + ICU IELSR allocator.
@ k_ra8_isr_prio_default
Middle priority.
Definition ra8_isr.h:107
ra8_err_t ra8_isr_init(void)
Initialise the ra8_isr table.
Definition ra8_isr.c:229
void ra8_isr_globals_enable(void)
Globally enable maskable interrupts (PRIMASK = 0).
Definition ra8_isr.c:439
ra8_err_t ra8_isr_register(ra8_elc_event_t event, ra8_isr_handler_t handler, void *ctx, uint8_t priority, uint16_t *out_slot)
Allocate an IELSR slot for an ELC event + handler.
Definition ra8_isr.c:296
Low Power Mode (LPM) HAL driver – public API.
ra8_err_t ra8_lpm_init(const ra8_lpm_config_t *cfg)
Initialise the LPM block from a config descriptor.
Definition ra8_lpm.c:358
@ k_ra8_lpm_clock_loco
Low-Speed On-Chip Oscillator.
Definition ra8_lpm.h:155
ra8_err_t ra8_lpm_enter_sleep(ra8_sleep_mode_t mode)
Programme LPSCR for mode and enter the requested sleep.
Definition ra8_lpm.c:735
ra8_err_t ra8_lpm_arm_wupen1_bits(uint32_t bits)
OR-in additional WUPEN1 bits without disturbing other sources.
Definition ra8_lpm.c:481
ra8_err_t ra8_lpm_set_clock_stop(ra8_lpm_clock_t clock, bool stop)
Set or clear the per-oscillator stop bit before sleep entry.
Definition ra8_lpm.c:661
Low Power Mode (LPM) register layout for the Renesas RA8D2.
@ k_ra8_lpm_ss2lp_default
SS2LP_0 – default mode.
@ k_ra8_sleep_mode_software_std
Software Standby (LPMD=0x5).
@ k_ra8_lpm_dcssmode_128us
128 us soft-start (cold-reset default).
@ k_ra8_lpm_wupen1_ulpt0u
ULP0UWUPEN @ bit 8.
SysTick-based tick counter, delay and timestamp helpers.
ra8_err_t ra8_time_init(uint32_t cpu_hz)
Initialise SysTick for a 1 kHz tick interrupt.
Definition ra8_time.c:59
Ultra-Low-Power Timer (ULPT) driver header.
ra8_err_t ra8_ulpt_get_status(uint8_t channel, uint8_t *out_mask)
Read ULPTCR status bits.
Definition ra8_ulpt.c:249
ra8_err_t ra8_ulpt_stop(uint8_t channel)
Stop a ULPT channel and confirm the counter has halted.
Definition ra8_ulpt.c:121
ra8_err_t ra8_ulpt_init(void)
Reset both ULPT channels to their power-on state.
Definition ra8_ulpt.c:64
ra8_err_t ra8_ulpt_start(uint8_t channel, uint32_t period)
Start a ULPT channel counting down from period.
Definition ra8_ulpt.c:93
@ k_ra8_ulpt_bit_tcstf
Count-status flag (read-only).
Configuration descriptor for ra8_lpm_init.
Definition ra8_lpm.h:96