ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_ulpt_regs.h
Go to the documentation of this file.
1
32
33#pragma once
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <stdint.h>
40
41#include "ra8_attributes.h"
42
47typedef enum : uintptr_t {
48 k_ra8_ulpt0_base_addr = 0x40220000UL,
49 k_ra8_ulpt1_base_addr = 0x40220100UL,
51
56typedef enum : uint16_t {
60
73
78typedef enum : uint8_t {
83
88typedef struct {
89 volatile uint32_t ULPTCNT;
90 volatile uint32_t ULPTCMA;
91 volatile uint32_t ULPTCMB;
92 volatile uint8_t ULPTCR;
93 volatile uint8_t ULPTMR1;
94 volatile uint8_t ULPTMR2;
95 volatile uint8_t ULPTMR3;
96 volatile uint8_t ULPTIOC;
98
105static inline volatile r_ulpt_regs_t* ra8_ulpt(uint8_t channel)
106{
107 if ((uint16_t)channel >= k_ra8_ulpt_channel_count) {
108 return nullptr;
109 }
110 return (volatile r_ulpt_regs_t*)(k_ra8_ulpt0_base_addr +
111 ((uintptr_t)channel * (uintptr_t)k_ra8_ulpt_channel_stride));
112}
113
114#ifdef __cplusplus
115}
116#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
ra8_ulpt_addr_t
Memory-mapped base addresses for ULPT.
@ k_ra8_ulpt1_base_addr
ULPT1 base (FSP R_ULPT1_BASE).
@ k_ra8_ulpt0_base_addr
ULPT0 base (FSP R_ULPT0_BASE).
ra8_ulptcr_bit_t
ULPTCR control-bit positions.
@ k_ra8_ulpt_bit_tstart
1 = start count, 0 = stop.
@ k_ra8_ulpt_bit_tstop
Forced stop bit.
@ k_ra8_ulpt_bit_tedgb
Edge detect flag B.
@ k_ra8_ulpt_bit_tcstf
Count-status flag (read-only).
@ k_ra8_ulpt_bit_tedga
Edge detect flag A.
@ k_ra8_ulpt_bit_tunf
Underflow flag.
ra8_ulpt_mask_t
ULPTCR bit masks.
@ k_ra8_ulpt_mask_tstart
TSTART bit.
@ k_ra8_ulpt_mask_tstop
TSTOP bit.
@ k_ra8_ulpt_mask_tcstf
TCSTF count-status flag (RO).
ra8_ulpt_limits_t
Channel count and stride.
@ k_ra8_ulpt_channel_count
ULPT0 and ULPT1.
@ k_ra8_ulpt_channel_stride
Bytes between channels.
static volatile r_ulpt_regs_t * ra8_ulpt(uint8_t channel)
Get pointer to ULPT channel channel.
Per-channel ULPT register window.
volatile uint8_t ULPTMR1
+0x0D Mode register 1.
volatile uint8_t ULPTIOC
+0x10 I/O control.
volatile uint8_t ULPTMR2
+0x0E Mode register 2.
volatile uint32_t ULPTCNT
+0x00 Counter / reload (32-bit).
volatile uint8_t ULPTMR3
+0x0F Mode register 3.
volatile uint32_t ULPTCMB
+0x08 Compare match B (32-bit).
volatile uint8_t ULPTCR
+0x0C Control register.
volatile uint32_t ULPTCMA
+0x04 Compare match A (32-bit).