144typedef enum : uint32_t {
152typedef enum : uint8_t {
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
ra8_err_t ra8_lpm_wait_for_opccr(uint32_t poll_limit)
Wait for OPCCR.OPCMTSF to clear (mode-transition complete).
ra8_err_t ra8_lpm_get_opccr(uint8_t *opccr)
Read OPCCR raw byte (OPCM[1:0] + OPCMTSF).
ra8_err_t ra8_lpm_init(const ra8_lpm_config_t *cfg)
Initialise the LPM block from a config descriptor.
ra8_lpm_pd_timeout_t
Poll bound for ra8_lpm_graphics_power_on flag waits.
@ k_ra8_lpm_pd_timeout_default
Default power-gate poll bound.
ra8_err_t ra8_lpm_clear_wupen1_bits(uint32_t bits)
AND-out WUPEN1 bits to disarm specific wake-up sources.
ra8_err_t ra8_lpm_snooze_set_request_sources(bool ulpt0_underflow, bool ulpt1_underflow, bool acmphs0)
Configure ULPT-driven snooze request sources.
ra8_err_t ra8_lpm_get_exit_cause(uint64_t *out)
Snapshot WUPEN0 / WUPEN1 into a single 64-bit word.
ra8_lpm_clock_t
Selector for ra8_lpm_set_clock_stop / ra8_lpm_get_clock_stop.
@ k_ra8_lpm_clock_loco
Low-Speed On-Chip Oscillator.
@ k_ra8_lpm_clock_sub
Sub-clock Oscillator.
@ k_ra8_lpm_clock_moco
Middle-Speed On-Chip Oscillator.
@ k_ra8_lpm_clock_main
Main Oscillator.
@ k_ra8_lpm_clock_count
RA8 lpm clock count.
@ k_ra8_lpm_clock_hoco
High-Speed On-Chip Oscillator.
ra8_err_t ra8_lpm_set_ram_retention(const ra8_lpm_ram_retention_t *cfg)
Programme PDRAMSCR0 / PDRAMSCR1 from a retention descriptor.
ra8_err_t ra8_lpm_prcr_relock(void)
Re-lock PRCR.PRC1 after protected writes.
ra8_err_t ra8_lpm_set_dpsiegr(ra8_lpm_dpsier_idx_t idx, uint8_t value)
Programme DPSIEGR0..2 (deep-standby IRQ edge polarity).
ra8_err_t ra8_lpm_enter_deep_standby(void)
Convenience wrapper – enter Deep Software Standby mode 1.
ra8_err_t ra8_lpm_enter_sleep(ra8_sleep_mode_t mode)
Programme LPSCR for mode and enter the requested sleep.
ra8_err_t ra8_lpm_get_clock_stop(ra8_lpm_clock_t clock, bool *stop)
Read the per-oscillator stop bit.
ra8_err_t ra8_lpm_snooze_set_end_sources(bool ulpt0, bool ulpt1, bool usbfs, bool usbhs)
Configure end-of-snooze sources via DPSIER3 (ULPT/USB hooks).
ra8_err_t ra8_lpm_arm_wupen0_bits(uint32_t bits)
OR-in additional WUPEN0 bits without disturbing other sources.
ra8_err_t ra8_lpm_graphics_power_on(uint32_t timeout_iters)
Power the graphics domain on (DRW / GLCDC / MIPI DSI+CSI / VIN).
ra8_err_t ra8_lpm_clear_dpsifr(ra8_lpm_dpsier_idx_t idx)
Clear DPSIFR0..3 so a stale flag does not cancel deep standby.
ra8_err_t ra8_lpm_arm_wupen1_bits(uint32_t bits)
OR-in additional WUPEN1 bits without disturbing other sources.
ra8_err_t ra8_lpm_deinit(void)
Restore SBYCR / DPSBYCR / LPSCR / SSCR1 to cold-reset defaults.
ra8_err_t ra8_lpm_get_status(uint32_t *out)
Read LPM status (SBYCR | DPSBYCR | LPSCR | SSCR1) packed.
ra8_err_t ra8_lpm_prcr_unlock(void)
Unlock PRCR.PRC1 to permit writes to LPM control registers.
ra8_err_t ra8_lpm_set_clock_stop(ra8_lpm_clock_t clock, bool stop)
Set or clear the per-oscillator stop bit before sleep entry.
ra8_err_t ra8_lpm_arm_dpsier(ra8_lpm_dpsier_idx_t idx, uint8_t value)
Programme the per-byte DPSIER0..3 enable byte directly.
ra8_err_t ra8_lpm_set_wakeup_sources(uint32_t wupen0, uint32_t wupen1)
Programme the raw WUPEN0 / WUPEN1 masks.
ra8_err_t ra8_lpm_get_dpsi_state(uint8_t enables[4], uint8_t flags[4], uint8_t edges[3])
Read DPSIER0..3 + DPSIFR0..3 + DPSIEGR0..2 into a buffer.
ra8_err_t ra8_lpm_clear_wupen0_bits(uint32_t bits)
AND-out WUPEN0 bits to disarm specific wake-up sources.
ra8_err_t ra8_lpm_set_ldo_standby(const ra8_lpm_ldo_cfg_t *cfg)
Programme PLL1LDOCR / PLL2LDOCR / HOCOLDOCR SKEEP bits.
Low Power Mode (LPM) register layout for the Renesas RA8D2.
ra8_lpm_sscr1_ss2lp_t
SSCR1.SS2LP encoding (HUM Ch 11.2.19 p 456).
ra8_sleep_mode_t
Software-selectable sleep modes (LPSCR.LPMD encoding).
ra8_lpm_dcssmode_t
DPSBYCR.DCSSMODE encoding (HUM Ch 11.2.21 p 458).
ra8_lpm_dpsier_idx_t
Selector for DPSIER0..3 / DPSIFR0..3 / DPSIEGR0..2 helpers (HUM Ch 11.2.22..36 p 459....
ra8_lpm_ldo_state_t
LDOCR.SKEEP encoding for ra8_lpm_set_ldo_standby.
Configuration descriptor for ra8_lpm_init.
bool opa_bus_keep
SBYCR.OPE – keep bus signals driven.
ra8_lpm_dcssmode_t dcdc_softstart
DCSSMODE encoding (k_ra8_lpm_dcssmode_*).
bool io_port_keep
DPSBYCR.IOKEEP – retain IOs across DSBY.
bool sscr_fast_return
SSCR1.SS2FR – speed up wake from SSTBY.
ra8_lpm_sscr1_ss2lp_t sscr_low_power
SSCR1.SS2LP encoding.
LDO standby retention selection (HUM 11.2.1 p 436).
ra8_lpm_ldo_state_t pll2
PLL2 LDO state in standby.
ra8_lpm_ldo_state_t pll1
PLL1 LDO state in standby.
ra8_lpm_ldo_state_t hoco
HOCO LDO state in standby.
RAM retention configuration (HUM 11.2.16 / 11.2.17).
bool cpu0_tcm_keep
PDRAMSCR1.RKEEP0.
bool cpu1_tcm_keep
PDRAMSCR1.RKEEP1 (dual-core only).
uint16_t pdramscr0_bits
Raw PDRAMSCR0 RKEEP[12:0] value.