ra8_board_ek_ra8d2_audio_usb.c

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#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_board_ek_ra8d2_audio_usb_internal.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_i2c.h"
#include "ra8_mpc.h"
#include "ra8_mstp.h"
#include "ra8_pfs_regs.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_ssie.h"
#include "ra8_time.h"
#include "ra8_usb.h"
 
/* =============================================================================
 * 4. Audio CODEC (UM Table 32, page 38)
 * =============================================================================
 */

static bool s_audio_initialized = false;

typedef enum : uint8_t {
  k_ra8_audio_bits_8  = 8U,  
  k_ra8_audio_bits_16 = 16U, 
  k_ra8_audio_bits_18 = 18U, 
  k_ra8_audio_bits_20 = 20U, 
  k_ra8_audio_bits_22 = 22U, 
  k_ra8_audio_bits_24 = 24U, 
  k_ra8_audio_bits_32 = 32U, 
} ra8_audio_bit_depth_t;

typedef enum : uint8_t {
  k_ra8_audio_channels_mono   = 1U, 
  k_ra8_audio_channels_stereo = 2U, 
} ra8_audio_channels_t;

typedef enum : uint8_t {
  k_ra8_audio_samples_per_word = 2U, 
} ra8_audio_pack_t;
 
/* Map ``bit_depth`` (significant bits) to SSIE DWL / SWL pair -- see implementation for details. */
RA8_INTERNAL static ra8_err_t internal_audio_bits_to_word(uint8_t                 bit_depth,
                                                          ra8_ssie_data_word_t*   out_dwl,
                                                          ra8_ssie_system_word_t* out_swl)
{
  switch ((ra8_audio_bit_depth_t)bit_depth) {
    case k_ra8_audio_bits_8:
      *out_dwl = k_ra8_ssie_dwl_8;
      *out_swl = k_ra8_ssie_swl_8;
      return k_ra8_ok;
    case k_ra8_audio_bits_16:
      *out_dwl = k_ra8_ssie_dwl_16;
      *out_swl = k_ra8_ssie_swl_16;
      return k_ra8_ok;
    case k_ra8_audio_bits_18:
      *out_dwl = k_ra8_ssie_dwl_18;
      *out_swl = k_ra8_ssie_swl_24;
      return k_ra8_ok;
    case k_ra8_audio_bits_20:
      *out_dwl = k_ra8_ssie_dwl_20;
      *out_swl = k_ra8_ssie_swl_24;
      return k_ra8_ok;
    case k_ra8_audio_bits_22:
      *out_dwl = k_ra8_ssie_dwl_22;
      *out_swl = k_ra8_ssie_swl_24;
      return k_ra8_ok;
    case k_ra8_audio_bits_24:
      *out_dwl = k_ra8_ssie_dwl_24;
      *out_swl = k_ra8_ssie_swl_24;
      return k_ra8_ok;
    case k_ra8_audio_bits_32:
      *out_dwl = k_ra8_ssie_dwl_32;
      *out_swl = k_ra8_ssie_swl_32;
      return k_ra8_ok;
    default:
      return k_ra8_err_invalid_arg;
  }
}
 
/* Route the six DA7212 audio pins (4 SSIE + 2 IIC) to their alt fns -- see implementation for details. */
RA8_INTERNAL static ra8_err_t internal_audio_route_pins(void)
{
  /* k_ra8_psel_ssie comes from HUM Ch 19 PFS PSEL field. MCLK on PD06
   * stays in GPIO mode -- the application picks SSIE EXTAL or CGC
   * clock-out explicitly. */
  const struct {
    ra8_port_pin_t pin;   
    ra8_psel_t     psel;  
    const char*    owner; 
  } routes[] = {
    {(ra8_port_pin_t)k_ra8_board_audio_pin_bclk, k_ra8_psel_ssie, "ra8_board.audio.bclk"},
    {(ra8_port_pin_t)k_ra8_board_audio_pin_wclk, k_ra8_psel_ssie, "ra8_board.audio.wclk"},
    {(ra8_port_pin_t)k_ra8_board_audio_pin_datin, k_ra8_psel_ssie, "ra8_board.audio.datin"},
    {(ra8_port_pin_t)k_ra8_board_audio_pin_datout, k_ra8_psel_ssie, "ra8_board.audio.datout"},
    {(ra8_port_pin_t)k_ra8_board_audio_pin_i2c_sda, k_ra8_psel_iic, "ra8_board.audio.i2c.sda"},
    {(ra8_port_pin_t)k_ra8_board_audio_pin_i2c_scl, k_ra8_psel_iic, "ra8_board.audio.i2c.scl"},
  };
  for (uint32_t i = 0U; i < sizeof(routes) / sizeof(routes[0]); ++i) {
    const ra8_err_t err = ra8_pfs_route_peripheral(routes[i].pin, routes[i].psel, routes[i].owner);
    if (err != k_ra8_ok) {
      return err;
    }
  }
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_ssie_cfg_t internal_audio_build_ssie_cfg(uint8_t                channels,
                                                                 ra8_ssie_data_word_t   dwl,
                                                                 ra8_ssie_system_word_t swl)
{
  return (ra8_ssie_cfg_t){
    .role          = k_ra8_ssie_role_controller,
    .format        = (channels == (uint8_t)k_ra8_audio_channels_mono) ? k_ra8_ssie_format_monaural
                                                                      : k_ra8_ssie_format_i2s,
    .data_word     = dwl,
    .system_word   = swl,
    .bclk_div      = k_ra8_ssie_bclk_div_4,
    .use_gpt_clk   = false,
    .long_frame    = false,
    .bckp_rising   = false,
    .lrckp_low     = false,
    .spdp_high     = false,
    .byte_swap     = false,
    .lr_continue   = false,
    .bck_idle_stop = false,
    .enable_aucke  = true,
    .tx_threshold  = 0U,
    .rx_threshold  = 0U,
  };
}
 
ra8_err_t ra8_board_audio_init(uint32_t sample_rate_hz, uint8_t bit_depth, uint8_t channels)
{
  if (sample_rate_hz == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (channels != (uint8_t)k_ra8_audio_channels_mono &&
      channels != (uint8_t)k_ra8_audio_channels_stereo) {
    return k_ra8_err_invalid_arg;
  }
  ra8_ssie_data_word_t   dwl  = k_ra8_ssie_dwl_16;
  ra8_ssie_system_word_t swl  = k_ra8_ssie_swl_16;
  ra8_err_t              berr = internal_audio_bits_to_word(bit_depth, &dwl, &swl);
  if (berr != k_ra8_ok) {
    return berr;
  }
 
  /* Step 1: route the four DAI pins to SSIE0 + the I2C control pair
   * to IIC1 (UM Table 32 p 38). */
  ra8_err_t rerr = internal_audio_route_pins();
  if (rerr != k_ra8_ok) {
    return rerr;
  }
 
  /* Step 2: bring up SSIE0 in I2S controller mode. */
  (void)sample_rate_hz;
  const ra8_ssie_cfg_t cfg  = internal_audio_build_ssie_cfg(channels, dwl, swl);
  const ra8_err_t      serr = ra8_ssie_init((uint8_t)k_ra8_board_audio_ssie_channel, &cfg);
  if (serr != k_ra8_ok) {
    return k_ra8_err_hw_init_failed;
  }
  s_audio_initialized = true;
  return k_ra8_ok;
}
 
ra8_err_t ra8_board_audio_play_sample_block(const int16_t* buf, uint32_t len)
{
  if (buf == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (len == 0U || (len % (uint32_t)k_ra8_audio_samples_per_word) != 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (!s_audio_initialized) {
    return k_ra8_err_not_initialized;
  }
  /* Two int16_t samples (one stereo frame) pack into one 32-bit SSIE
   * FIFO word; len is guaranteed even by the check above. The buffer
   * is a contiguous PCM stream the SSIE FIFO consumes 32 bits at a
   * time. Reinterpret via uintptr_t so we neither (a) double-hop
   * through void* (bugprone-casting-through-void) nor (b) trip
   * cast-align by going int16_t* -> uint32_t* directly. The caller
   * contract requires ``buf`` to be 32-bit aligned (one stereo frame
   * naturally aligns); see ra8_board_audio_play_sample_block docs. */
  const uint32_t        words   = len / (uint32_t)k_ra8_audio_samples_per_word;
  const uintptr_t       addr    = (uintptr_t)buf;
  const uint32_t* const packed  = (const uint32_t*)addr;
  uint16_t              written = 0U;
  const ra8_err_t       err     = ra8_ssie_write_buffer((uint8_t)k_ra8_board_audio_ssie_channel,
                                                        packed,
                                                        (uint16_t)words,
                                                        &written);
  if (err != k_ra8_ok) {
    return err;
  }
  if (written != (uint16_t)words) {
    return k_ra8_err_hw_timeout;
  }
  return k_ra8_ok;
}
 
/* =============================================================================
 * 7. USB stubs (HS HAL not yet wired to BSP)
 * =============================================================================
 */

volatile uint32_t g_usbhs_probe = 0U;

typedef enum : uint32_t {
  k_usbhs_probe_pre_pll_enable    = 1U, 
  k_usbhs_probe_pre_mstp_init     = 2U, 
  k_usbhs_probe_pre_mstp_enable   = 3U, 
  k_usbhs_probe_pre_usb_dev_init  = 4U, 
  k_usbhs_probe_post_usb_dev_init = 5U, 
} usbhs_probe_step_t;

RA8_INTERNAL static ra8_err_t internal_usbhs_clock_and_mstp(void)
{
  g_usbhs_probe = (uint32_t)k_usbhs_probe_pre_pll_enable;
  ra8_err_t err = ra8_cgc_usbhs_pll_enable();
  if (err != k_ra8_ok) {
    return err;
  }
  /* DO NOT call ra8_mstp_init() here -- it gates ALL modules (IOPORT,
   * SCI, etc.) and the chip faults trying to access already-running
   * peripherals. ra8_mstp_init must run exactly once per boot, before
   * any peripheral is brought up; the boot-time path handles that.
   * ra8_mstp_enable below uses the existing ref-counted state. */
  g_usbhs_probe = (uint32_t)k_usbhs_probe_pre_mstp_enable;
  return ra8_mstp_enable(k_ra8_mstp_usbhs);
}
 
/* =============================================================================
 * U15 PI4IOE5V6408 I/O expander -- SW4 override (J7 USB role select etc.)
 *
 * EK-RA8D2 v1 UM Rev 1.01 Section 5.5.3 + Section 4 p 16:
 *   "The EK-RA8D2 features an I2C I/O Port Expander (PI4IOE5V6408) at
 *    U15 which has the I2C address 0x43. The port expander is connected
 *    to the configuration switches SW4 and allows the settings to be
 *    read (when the I/O expander port is set to input) or overridden
 *    (when the I/O expander port is set to output) by software."
 *
 * Register map and polarity convention come from Renesas's reference
 * driver in ``ra-fsp-examples/ek_ra8t2/board_cfg_switch.c`` (the EK-RA8T2
 * sister board uses an identical wiring).
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_board_io_expander_addr = 0x43U, 
} ra8_board_io_expander_addr_t;

typedef enum : uint8_t {
  k_ra8_board_pi4ioe_reg_devid     = 0x01U, 
  k_ra8_board_pi4ioe_reg_iodir     = 0x03U, 
  k_ra8_board_pi4ioe_reg_output    = 0x05U, 
  k_ra8_board_pi4ioe_reg_hiz       = 0x07U, 
  k_ra8_board_pi4ioe_reg_pud_sel   = 0x0DU, 
  k_ra8_board_pi4ioe_reg_input_lvl = 0x0FU, 
} ra8_board_pi4ioe_reg_t;

typedef enum : uint8_t {
  k_ra8_board_pi4ioe_iodir_all_outputs = 0xFFU, 
  k_ra8_board_pi4ioe_output_all_high   = 0xFFU, 
  k_ra8_board_pi4ioe_hiz_none          = 0x00U, 
} ra8_board_pi4ioe_magic_t;

typedef enum : uint32_t {
  k_ra8_board_io_expander_bus_hz   = 100000U,   
  k_ra8_board_io_expander_pclkb_hz = 62500000U, 
} ra8_board_io_expander_clk_t;

typedef enum : uint8_t {
  k_ra8_board_io_expander_iic_channel = 1U, 
} ra8_board_io_expander_channel_t;

static const ra8_port_pin_t s_ra8_board_io_expander_pin_scl =
  (ra8_port_pin_t)RA8_PIN(k_ra8_port_5, k_ra8_pin_12); 
static const ra8_port_pin_t s_ra8_board_io_expander_pin_sda =
  (ra8_port_pin_t)RA8_PIN(k_ra8_port_5, k_ra8_pin_11); 

static const ra8_port_pin_t s_ra8_board_io_expander_pin_pullup_a =
  (ra8_port_pin_t)RA8_PIN(k_ra8_port_1, k_ra8_pin_9); 
static const ra8_port_pin_t s_ra8_board_io_expander_pin_pullup_b =
  (ra8_port_pin_t)RA8_PIN(k_ra8_port_3, k_ra8_pin_11); 

typedef enum : uint32_t {
  k_ra8_board_i2c_recover_pulses = 9U,    
  k_ra8_board_i2c_recover_spins  = 2000U, 
} ra8_board_i2c_recover_t;
 
/* internal_io_expander_write_reg -- see implementation for details. */
RA8_INTERNAL static ra8_err_t internal_io_expander_write_reg(uint8_t reg, uint8_t val)
{
  const uint8_t buf[2] = {reg, val};
  /* Each PI4IOE5V6408 register write is a complete START..STOP
   * transaction. Chaining them with repeated-START (send_stop = false)
   * leaves the bus held and the device's command parser misaligned on the
   * third back-to-back write, so always close the transaction with a STOP. */
  return ra8_i2c_write((uint8_t)k_ra8_board_io_expander_iic_channel,
                       (uint8_t)k_ra8_board_io_expander_addr,
                       buf,
                       sizeof(buf),
                       true);
}

static volatile uint32_t s_io_expander_probe = 0U;

typedef enum : uint32_t {
  k_io_exp_probe_pre_pfs       = 1U, 
  k_io_exp_probe_pre_init      = 2U, 
  k_io_exp_probe_pre_write_out = 3U, 
  k_io_exp_probe_pre_write_hiz = 4U, 
  k_io_exp_probe_pre_write_dir = 5U, 
  k_io_exp_probe_success       = 6U, 
} io_exp_probe_step_t;

RA8_INTERNAL static void internal_io_expander_bus_settle(void)
{
  for (volatile uint32_t i = 0U; i < (uint32_t)k_ra8_board_i2c_recover_spins; i++) {
    __asm__ volatile("nop");
  }
}

RA8_INTERNAL static ra8_err_t internal_io_expander_bus_recover(void)
{
  const ra8_port_pin_t scl = s_ra8_board_io_expander_pin_scl;
  const ra8_port_pin_t sda = s_ra8_board_io_expander_pin_sda;
  ra8_err_t            err = ra8_gpio_output_init(scl, k_ra8_level_high);
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_gpio_input_init(sda, k_ra8_pull_up);
  if (err != k_ra8_ok) {
    (void)ra8_gpio_release(scl);
    return err;
  }
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_board_i2c_recover_pulses; i++) {
    ra8_level_t     sda_lvl = k_ra8_level_low;
    const ra8_err_t rd      = ra8_gpio_read(sda, &sda_lvl);
    if (rd == k_ra8_ok) {
      if (sda_lvl == k_ra8_level_high) {
        break; /* peripheral released SDA -- bus is free */
      }
    }
    (void)ra8_gpio_write(scl, k_ra8_level_low);
    internal_io_expander_bus_settle();
    (void)ra8_gpio_write(scl, k_ra8_level_high);
    internal_io_expander_bus_settle();
  }
  /* Frame a STOP (SDA low->high while SCL high) to end any partial frame,
   * then release both pins for the IIC mux to re-claim. */
  (void)ra8_gpio_release(sda);
  (void)ra8_gpio_output_init(sda, k_ra8_level_low);
  internal_io_expander_bus_settle();
  (void)ra8_gpio_write(scl, k_ra8_level_high);
  (void)ra8_gpio_write(sda, k_ra8_level_high);
  internal_io_expander_bus_settle();
  (void)ra8_gpio_release(sda);
  (void)ra8_gpio_release(scl);
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_err_t internal_io_expander_enable_pullups(void)
{
  ra8_err_t err = ra8_gpio_output_init(s_ra8_board_io_expander_pin_pullup_a, k_ra8_level_high);
  if (err != k_ra8_ok) {
    return err;
  }
  return ra8_gpio_output_init(s_ra8_board_io_expander_pin_pullup_b, k_ra8_level_high);
}

RA8_INTERNAL static ra8_err_t internal_io_expander_route_pins(void)
{
  ra8_err_t err = ra8_pfs_route_peripheral(s_ra8_board_io_expander_pin_scl,
                                           k_ra8_psel_iic,
                                           "ra8_board.io_exp.scl1");
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_mpc_set_open_drain(k_ra8_port_5, k_ra8_pin_12, true);
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_pfs_route_peripheral(s_ra8_board_io_expander_pin_sda,
                                 k_ra8_psel_iic,
                                 "ra8_board.io_exp.sda1");
  if (err != k_ra8_ok) {
    return err;
  }
  return ra8_mpc_set_open_drain(k_ra8_port_5, k_ra8_pin_11, true);
}

RA8_INTERNAL static ra8_err_t internal_io_expander_program_u15(uint8_t output_byte,
                                                               uint8_t output_mask)
{
  s_io_expander_probe = (uint32_t)k_io_exp_probe_pre_write_out;
  ra8_err_t err =
    internal_io_expander_write_reg((uint8_t)k_ra8_board_pi4ioe_reg_output, output_byte);
  if (err != k_ra8_ok) {
    return err;
  }
  s_io_expander_probe = (uint32_t)k_io_exp_probe_pre_write_hiz;
  err                 = internal_io_expander_write_reg((uint8_t)k_ra8_board_pi4ioe_reg_hiz,
                                                       (uint8_t)k_ra8_board_pi4ioe_hiz_none);
  if (err != k_ra8_ok) {
    return err;
  }
  s_io_expander_probe = (uint32_t)k_io_exp_probe_pre_write_dir;
  return internal_io_expander_write_reg((uint8_t)k_ra8_board_pi4ioe_reg_iodir, output_mask);
}

RA8_INTERNAL static ra8_err_t internal_io_expander_apply_mask(uint8_t output_byte,
                                                              uint8_t output_mask)
{
  /* Step -1: clock out any wedged peripheral (stuck SDA) before touching
   * the bus, so a prior aborted transfer cannot deadlock every START. */
  ra8_err_t err = internal_io_expander_bus_recover();
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Step 0: drive P109/P311 high so the SCL1/SDA1 bus has pull-ups
   * (EK-RA8D2 v1 UM Table 23). Without this the open-drain bus floats
   * and U15 cannot ACK. */
  err = internal_io_expander_enable_pullups();
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Step 1: route P512 -> SCL1 and P511 -> SDA1 with NCODR on both
   * (HUM Ch 20.6 PSEL table p 859). */
  s_io_expander_probe = (uint32_t)k_io_exp_probe_pre_pfs;
  err                 = internal_io_expander_route_pins();
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Step 2: bring RIIC channel 1 up at 100 kHz. ra8_i2c_init ungates
   * the per-channel MSTP gate (IIC1 = MSTPB8) itself, so no separate
   * MSTP enable is needed here. */
  s_io_expander_probe     = (uint32_t)k_io_exp_probe_pre_init;
  const ra8_i2c_cfg_t cfg = {
    .bus_hz   = (uint32_t)k_ra8_board_io_expander_bus_hz,
    .pclkb_hz = (uint32_t)k_ra8_board_io_expander_pclkb_hz,
  };
  err = ra8_i2c_init((uint8_t)k_ra8_board_io_expander_iic_channel, &cfg);
  if (err != k_ra8_ok) {
    return err;
  }
 
  /* Step 4: program U15 in FSP-reference order. */
  err = internal_io_expander_program_u15(output_byte, output_mask);
  if (err != k_ra8_ok) {
    return err;
  }
  s_io_expander_probe = (uint32_t)k_io_exp_probe_success;
  return k_ra8_ok;
}
 
ra8_err_t ra8_board_io_expander_set_usbhs_device_mode(void)
{
  return internal_io_expander_apply_mask((uint8_t)k_ra8_board_pi4ioe_output_all_high,
                                         (uint8_t)k_ra8_board_pi4ioe_iodir_all_outputs);
}

ra8_err_t ra8_board_io_expander_set_usbhs_host_mode(void)
{
  return internal_io_expander_apply_mask((uint8_t)k_ra8_board_pi4ioe_output_usbhs_host,
                                         (uint8_t)k_ra8_board_pi4ioe_iodir_all_outputs);
}

ra8_err_t ra8_board_io_expander_apply_project_sw4_defaults(void)
{
  return internal_io_expander_apply_mask((uint8_t)k_ra8_board_pi4ioe_output_project_default,
                                         (uint8_t)k_ra8_board_pi4ioe_iodir_all_outputs);
}
 
ra8_err_t ra8_board_io_expander_apply_sw4(uint8_t output_byte)
{
  return internal_io_expander_apply_mask(output_byte,
                                         (uint8_t)k_ra8_board_pi4ioe_iodir_all_outputs);
}
 
ra8_err_t ra8_board_io_expander_apply_sw4_mask(uint8_t output_byte, uint8_t output_mask)
{
  return internal_io_expander_apply_mask(output_byte, output_mask);
}
 
ra8_err_t ra8_board_io_expander_set_octospi_active(void)
{
  return internal_io_expander_apply_mask((uint8_t)k_ra8_board_pi4ioe_output_octospi_active,
                                         (uint8_t)k_ra8_board_pi4ioe_iodir_all_outputs);
}

volatile uint32_t g_usbhs_role_pin_probe = 0U;

volatile uint32_t g_usbhs_role_pin_err = 0U;

typedef enum : uint32_t {
  k_usbhs_role_probe_pre_init  = 1U, 
  k_usbhs_role_probe_post_init = 2U, 
  k_usbhs_role_probe_success   = 3U, 
} usbhs_role_probe_step_t;

RA8_INTERNAL static ra8_err_t internal_usbhs_role_select_device(void)
{
  g_usbhs_role_pin_probe = (uint32_t)k_usbhs_role_probe_pre_init;
  /* PD07 (port 13, pin 7). The ra8_port_pin_t enum only pre-defines LED
   * pins, so any other packed value lands outside the enumerator set
   * and trips clang-analyzer EnumCastOutOfRange; suppress in the same
   * pattern used elsewhere in this file for board-specific pins. */
  const ra8_port_pin_t pd07 = (ra8_port_pin_t)RA8_PIN(k_ra8_port_13, k_ra8_pin_7);
  const ra8_err_t      err  = ra8_gpio_output_init(pd07, k_ra8_level_low);
  g_usbhs_role_pin_err      = (uint32_t)err;
  g_usbhs_role_pin_probe    = (uint32_t)k_usbhs_role_probe_post_init;
  if (err == k_ra8_ok) {
    g_usbhs_role_pin_probe = (uint32_t)k_usbhs_role_probe_success;
  }
  return err;
}
 
ra8_err_t ra8_board_usbhs_device_init(void)
{
  /* HUM Ch 9 (CGC) USBCKCR p 365 + HUM Ch 11 (MSTP) MSTPCRB12 p 469
   * stage the PHY clock and ungate the controller block; then the
   * generic device-mode entry in libs/ra8_hal/inc/ra8_usb.h drives
   * SYSCFG.SCKE / USBE / HSE and arms the device IRQ set.
   *
   * EK-RA8D2 v1 UM Rev 1.01 Section 6.2 p 34 ("USB High Speed"): J7's
   * role is selected by the MCU GPIO PD07 -- LOW = Device, HIGH = Host.
   * Drive PD07 low directly (no U15 I/O-expander dependency required;
   * U15 is only an SW4 override path, see Section 4.3.4 p 16 / Table 23
   * pullup-config p 31). The U15 helper is invoked best-effort below
   * for boards where PD07 alone is insufficient (e.g. SW4-8 mechanical
   * position contradicts the firmware intent), but its failure is
   * non-fatal because PD07 already strapped the role line. */
  const ra8_err_t pd07_err = internal_usbhs_role_select_device();
  if (pd07_err != k_ra8_ok) {
    return pd07_err;
  }
 
  /* Best-effort U15 override (logged via s_io_expander_probe). The U15
   * I2C path may NACK if SW4-5 is OFF (I2C/I3C-Select strap routes the
   * shared bus elsewhere) -- non-fatal because PD07 already strapped
   * the role. */
  const ra8_err_t io_err = ra8_board_io_expander_set_usbhs_device_mode();
  (void)io_err;
  ra8_err_t err = internal_usbhs_clock_and_mstp();
  if (err != k_ra8_ok) {
    return err;
  }
  g_usbhs_probe    = (uint32_t)k_usbhs_probe_pre_usb_dev_init;
  ra8_err_t rc_dev = ra8_usb_device_init(k_ra8_usb_speed_hs);
  g_usbhs_probe    = (uint32_t)k_usbhs_probe_post_usb_dev_init;
  return rc_dev;
}
 
ra8_err_t ra8_board_usbhs_host_init(void)
{
  /* Symmetric to ra8_board_usbhs_device_init. EK-RA8D2 v1 UM Rev 1.01
   * Table 28 lists USBHS_VBUSEN / USBHS_OVRCUR as PHY-controller
   * pins not routed to RA8D2 port pins, so VBUS sourcing is left to
   * the on-board USB-PD controller. ra8_usb_host_init drives
   * SYSCFG.DCFM=1 / DRPD=1 / USBE=1 plus the DCP setup. */
  ra8_err_t err = internal_usbhs_clock_and_mstp();
  if (err != k_ra8_ok) {
    return err;
  }
  return ra8_usb_host_init(k_ra8_usb_speed_hs);
}