ra8_i2c_config.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_i2c.h"
#include "ra8_i2c_internal.h"
#include "ra8_i2c_regs.h"
#include "ra8_log.h"
#include "ra8_mstp.h"

typedef enum : uint32_t {
  k_ra8_i2c_br_field_max = 0x1FU,
  k_ra8_i2c_br_reserved_hi = 0xE0U,
  k_ra8_i2c_cks_max = 7U,
  k_ra8_i2c_period_split = 2U,
} ra8_i2c_brate_t;

RA8_INTERNAL static ra8_mstp_t internal_i2c_mstp_id(uint8_t channel)
{
  if (channel == 0U) {
    return k_ra8_mstp_iic0;
  }
  if (channel == 1U) {
    return k_ra8_mstp_iic1;
  }
  return k_ra8_mstp_iic2;
}

RA8_INTERNAL static uint8_t internal_i2c_pick_cks(uint32_t* total)
{
  uint32_t cks = 0U;
  for (uint32_t i = 0U; i <= (uint32_t)k_ra8_i2c_cks_max; i++) {
    const uint32_t half = *total / (uint32_t)k_ra8_i2c_period_split;
    if (half <= ((uint32_t)k_ra8_i2c_br_field_max + 1U)) {
      break;
    }
    cks    = i + 1U;
    *total = *total >> 1U;
  }
  if (cks > (uint32_t)k_ra8_i2c_cks_max) {
    cks = (uint32_t)k_ra8_i2c_cks_max;
  }
  return (uint8_t)cks;
}

RA8_INTERNAL static uint8_t internal_i2c_clamp_half(uint32_t total)
{
  uint32_t half = total / (uint32_t)k_ra8_i2c_period_split;
  if (half == 0U) {
    half = 1U;
  }
  uint32_t field = half - 1U;
  if (field > (uint32_t)k_ra8_i2c_br_field_max) {
    field = (uint32_t)k_ra8_i2c_br_field_max;
  }
  return (uint8_t)field;
}

RA8_INTERNAL static ra8_err_t internal_i2c_bitrate(uint32_t bus_hz,
                                                   uint32_t pclkb_hz,
                                                   uint8_t* out_cks,
                                                   uint8_t* out_brh,
                                                   uint8_t* out_brl)
{
  RA8_CHECK_NULL_PTR(out_cks, g_i2c_tag, "bitrate: out_cks");
  RA8_CHECK_NULL_PTR(out_brh, g_i2c_tag, "bitrate: out_brh");
  if (priv_ra8_i2c_internal_clk_invalid(bus_hz, pclkb_hz)) {
    return k_ra8_err_invalid_arg;
  }
 
  /* Each transferred bit needs (BRH+1)+(BRL+1) IICphi cycles. Pick the
   * smallest CKS that fits both half-periods in the 5-bit field, then
   * derive the clamped half-period count for ICBRL / ICBRH. */
  uint32_t      total = pclkb_hz / bus_hz;
  const uint8_t cks   = internal_i2c_pick_cks(&total);
  const uint8_t field = internal_i2c_clamp_half(total);
 
  *out_cks = cks;
  *out_brh = (uint8_t)((uint32_t)k_ra8_i2c_br_reserved_hi | (uint32_t)field);
  *out_brl = (uint8_t)((uint32_t)k_ra8_i2c_br_reserved_hi | (uint32_t)field);
  return k_ra8_ok;
}

RA8_INTERNAL static uint8_t internal_i2c_decode_errors(uint8_t icsr2)
{
  uint8_t mask = (uint8_t)k_ra8_i2c_err_none;
  if ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_al) != 0U) {
    mask |= (uint8_t)k_ra8_i2c_err_arb_lost;
  }
  if ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_nackf) != 0U) {
    mask |= (uint8_t)k_ra8_i2c_err_nack;
  }
  /* TMOF lives in ICSR2 bit 0; reuse the timeout mask via the position. */
  if ((icsr2 & (uint8_t)(1U << (uint8_t)k_ra8_i2c_icsr2_tmof_pos)) != 0U) {
    mask |= (uint8_t)k_ra8_i2c_err_timeout;
  }
  return mask;
}
 
/* =============================================================================
 * Init / deinit -- mirrors HUM Ch 39.3.2 "Initial Settings" p 2395.
 * =============================================================================
 */

RA8_INTERNAL static void internal_i2c_apply_init_regs(volatile r_i2c_regs_t* reg,
                                                      uint8_t                cks,
                                                      uint8_t                brh,
                                                      uint8_t                brl,
                                                      bool                   fast_plus)
{
  /* Initial-settings step 1 (Figure 39.5): ICE = 0, pins inactive.
   * HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1" p 2369 */
  reg->ICCR1 = 0U;
  /* Initial-settings step 2: IICRST = 1 (IIC reset, ICE still 0).
   * HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1" p 2369 */
  reg->ICCR1 = (uint8_t)k_ra8_i2c_msk_iccr1_iicrst;
  /* Initial-settings step 3: ICE = 1 (internal reset, pins active).
   * HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1" p 2369 */
  reg->ICCR1 = (uint8_t)((uint8_t)k_ra8_i2c_msk_iccr1_iicrst | (uint8_t)k_ra8_i2c_msk_iccr1_ice);
 
  /* HUM Ch 39.2.3 "ICMR1 : I2C Bus Mode Register 1 -- CKS[6:4]" p 2374 */
  reg->ICMR1 = (uint8_t)((uint32_t)cks << (uint32_t)k_ra8_i2c_icmr1_cks_pos);
  /* HUM Ch 39.2.15 "ICBRL : I2C Bus Bit Rate Low-Level Register" p 2391 */
  reg->ICBRL = brl;
  /* HUM Ch 39.2.16 "ICBRH : I2C Bus Bit Rate High-Level Register" p 2392 */
  reg->ICBRH = brh;
 
  /* Enable arbitration-lost detection, NACK transfer suspension, the SCL
   * synchronous circuit, and (for Fm+) the slope-control circuit.
   * HUM Ch 39.2.6 "ICFER : I2C Bus Function Enable Register" p 2378 */
  uint8_t icfer = (uint8_t)((uint8_t)k_ra8_i2c_msk_icfer_male | (uint8_t)k_ra8_i2c_msk_icfer_nacke |
                            (uint8_t)k_ra8_i2c_msk_icfer_scle);
  if (fast_plus) {
    icfer |= (uint8_t)k_ra8_i2c_msk_icfer_fmpe;
  }
  reg->ICFER = icfer;
 
  /* Initial-settings step 5: release the internal reset (IICRST = 0).
   * HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1" p 2369 */
  reg->ICCR1 = (uint8_t)k_ra8_i2c_msk_iccr1_ice;
}
 
ra8_err_t ra8_i2c_init(uint8_t channel, const ra8_i2c_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, g_i2c_tag, "i2c_init: cfg");
  uint8_t         cks    = 0U;
  uint8_t         brh    = 0U;
  uint8_t         brl    = 0U;
  const ra8_err_t br_err = internal_i2c_bitrate(cfg->bus_hz, cfg->pclkb_hz, &cks, &brh, &brl);
  RA8_RETURN_ON_ERROR(br_err, g_i2c_tag, "i2c_init: bitrate");
 
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
 
  const ra8_err_t mst_err = ra8_mstp_enable(internal_i2c_mstp_id(channel));
  RA8_RETURN_ON_ERROR(mst_err, g_i2c_tag, "i2c_init: mstp");
 
  internal_i2c_apply_init_regs(reg,
                               cks,
                               brh,
                               brl,
                               cfg->bus_hz >= (uint32_t)k_ra8_i2c_speed_fast_plus);
 
  s_i2c_state[channel].initialized = true;
  s_i2c_state[channel].bus_held    = false;
 
  ra8_log_info_val(g_i2c_tag, "i2c_init channel", (uint32_t)channel);
  return k_ra8_ok;
}
 
ra8_err_t ra8_i2c_deinit(uint8_t channel)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  /* ICE = 0: place the SCL/SDA pins back in the inactive state.
   * HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1" p 2369 */
  reg->ICCR1                       = 0U;
  s_i2c_state[channel].initialized = false;
  s_i2c_state[channel].bus_held    = false;
  return ra8_mstp_disable(internal_i2c_mstp_id(channel));
}
 
ra8_err_t ra8_i2c_set_clock(uint8_t channel, uint32_t bus_hz, uint32_t pclkb_hz)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  uint8_t         cks    = 0U;
  uint8_t         brh    = 0U;
  uint8_t         brl    = 0U;
  const ra8_err_t br_err = internal_i2c_bitrate(bus_hz, pclkb_hz, &cks, &brh, &brl);
  if (br_err != k_ra8_ok) {
    return br_err;
  }
  /* HUM Ch 39.2.3 "ICMR1 : I2C Bus Mode Register 1 -- CKS[6:4]" p 2374 */
  reg->ICMR1 = (uint8_t)(((uint32_t)reg->ICMR1 & ~((uint32_t)(uint8_t)k_ra8_i2c_cks_max
                                                   << (uint32_t)k_ra8_i2c_icmr1_cks_pos)) |
                         ((uint32_t)cks << (uint32_t)k_ra8_i2c_icmr1_cks_pos));
  /* HUM Ch 39.2.15 "ICBRL : I2C Bus Bit Rate Low-Level Register" p 2391 */
  reg->ICBRL = brl;
  /* HUM Ch 39.2.16 "ICBRH : I2C Bus Bit Rate High-Level Register" p 2392 */
  reg->ICBRH = brh;
  return k_ra8_ok;
}
 
/* =============================================================================
 * Status helpers.
 * =============================================================================
 */
 
ra8_err_t ra8_i2c_get_errors(uint8_t channel, uint8_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, g_i2c_tag, "i2c_get_errors: out_mask");
  volatile const r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
  *out_mask = internal_i2c_decode_errors(reg->ICSR2);
  return k_ra8_ok;
}
 
ra8_err_t ra8_i2c_clear_errors(uint8_t channel)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  enum : uint8_t {
    k_ra8_i2c_err_clear_mask =
      (uint8_t)((uint8_t)k_ra8_i2c_msk_icsr2_al | (uint8_t)k_ra8_i2c_msk_icsr2_nackf |
                (uint8_t)(1U << (uint8_t)
                            k_ra8_i2c_icsr2_tmof_pos)), 
  };
  /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2 -- W0C" p 2384 */
  reg->ICSR2 = (uint8_t)(reg->ICSR2 & (uint8_t)~(uint8_t)k_ra8_i2c_err_clear_mask);
  return k_ra8_ok;
}