ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_i2c_regs_t Struct Reference

Memory-mapped register block for one IIC channel. More...

#include <ra8_i2c_regs.h>

Data Fields

volatile uint8_t ICCR1
 +0x00 Bus Control Register 1 (HUM 39.2.1, p 2369).
volatile uint8_t ICCR2
 +0x01 Bus Control Register 2 (HUM 39.2.2, p 2371).
volatile uint8_t ICMR1
 +0x02 Bus Mode Register 1 (HUM 39.2.3, p 2374).
volatile uint8_t ICMR2
 +0x03 Bus Mode Register 2 (HUM 39.2.4, p 2375).
volatile uint8_t ICMR3
 +0x04 Bus Mode Register 3 (HUM 39.2.5, p 2376).
volatile uint8_t ICFER
 +0x05 Bus Function Enable (HUM 39.2.6, p 2378).
volatile uint8_t ICSER
 +0x06 Bus Status Enable (HUM 39.2.7, p 2380).
volatile uint8_t ICIER
 +0x07 Bus Interrupt Enable (HUM 39.2.8, p 2381).
volatile uint8_t ICSR1
 +0x08 Bus Status Register 1 (HUM 39.2.9, p 2382).
volatile uint8_t ICSR2
 +0x09 Bus Status Register 2 (HUM 39.2.10, p 2384).
volatile uint8_t SARL0
 +0x0A Peripheral Address L0 (HUM 39.2.13, p 2390).
volatile uint8_t SARU0
 +0x0B Peripheral Address U0 (HUM 39.2.14, p 2391).
volatile uint8_t SARL1
 +0x0C Peripheral Address L1 (HUM 39.2.13, p 2390).
volatile uint8_t SARU1
 +0x0D Peripheral Address U1 (HUM 39.2.14, p 2391).
volatile uint8_t SARL2
 +0x0E Peripheral Address L2 (HUM 39.2.13, p 2390).
volatile uint8_t SARU2
 +0x0F Peripheral Address U2 (HUM 39.2.14, p 2391).
volatile uint8_t ICBRL
 +0x10 Bit Rate Low-Level (HUM 39.2.15, p 2391).
volatile uint8_t ICBRH
 +0x11 Bit Rate High-Level (HUM 39.2.16, p 2392).
volatile uint8_t ICDRT
 +0x12 Transmit Data Register (HUM 39.2.17, p 2393).
volatile uint8_t ICDRR
 +0x13 Receive Data Register (HUM 39.2.18, p 2393).
volatile uint8_t ICWUR
 +0x14 Wakeup Unit Register (HUM 39.2.11, p 2388).
volatile uint8_t ICWUR2
 +0x15 Wakeup Unit Register 2 (HUM 39.2.12, p 2389).

Detailed Description

Memory-mapped register block for one IIC channel.

Layout matches HUM Ch 39.2 "Register Descriptions" (p 2369-2394). Every RIIC register is a single byte. The wakeup-unit registers (ICWUR / ICWUR2 at +0x14 / +0x15, IIC0 only) are reserved holes here – the controller-mode polling driver does not touch them.

Invariant
sizeof(r_i2c_regs_t) is 0x16 bytes, well within the 0x100 channel stride.

Definition at line 78 of file ra8_i2c_regs.h.

Field Documentation

◆ ICBRH

volatile uint8_t r_i2c_regs_t::ICBRH

+0x11 Bit Rate High-Level (HUM 39.2.16, p 2392).

Definition at line 96 of file ra8_i2c_regs.h.

Referenced by internal_i2c_apply_init_regs(), and ra8_i2c_set_clock().

◆ ICBRL

volatile uint8_t r_i2c_regs_t::ICBRL

+0x10 Bit Rate Low-Level (HUM 39.2.15, p 2391).

Definition at line 95 of file ra8_i2c_regs.h.

Referenced by internal_i2c_apply_init_regs(), and ra8_i2c_set_clock().

◆ ICCR1

volatile uint8_t r_i2c_regs_t::ICCR1

+0x00 Bus Control Register 1 (HUM 39.2.1, p 2369).

Definition at line 79 of file ra8_i2c_regs.h.

Referenced by internal_i2c_apply_init_regs(), and ra8_i2c_deinit().

◆ ICCR2

volatile uint8_t r_i2c_regs_t::ICCR2

+0x01 Bus Control Register 2 (HUM 39.2.2, p 2371).

Definition at line 80 of file ra8_i2c_regs.h.

Referenced by internal_i2c_busy_gate(), internal_i2c_restart(), internal_i2c_start(), internal_i2c_stop_request(), internal_i2c_wait_bus_free(), ra8_i2c_peripheral_dispatch(), and ra8_i2c_peripheral_poll().

◆ ICDRR

volatile uint8_t r_i2c_regs_t::ICDRR

+0x13 Receive Data Register (HUM 39.2.18, p 2393).

Definition at line 98 of file ra8_i2c_regs.h.

Referenced by internal_i2c_drain_rx(), internal_i2c_target_finish_tx(), priv_ra8_i2c_internal_target_drain_rx(), and ra8_i2c_peripheral_receive().

◆ ICDRT

volatile uint8_t r_i2c_regs_t::ICDRT

+0x12 Transmit Data Register (HUM 39.2.17, p 2393).

Definition at line 97 of file ra8_i2c_regs.h.

Referenced by internal_i2c_drain_tx(), internal_i2c_send_address(), and internal_i2c_target_fill_tx().

◆ ICFER

volatile uint8_t r_i2c_regs_t::ICFER

+0x05 Bus Function Enable (HUM 39.2.6, p 2378).

Definition at line 84 of file ra8_i2c_regs.h.

Referenced by internal_i2c_apply_init_regs().

◆ ICIER

volatile uint8_t r_i2c_regs_t::ICIER

+0x07 Bus Interrupt Enable (HUM 39.2.8, p 2381).

Definition at line 86 of file ra8_i2c_regs.h.

Referenced by ra8_i2c_peripheral_deinit(), and ra8_i2c_peripheral_init().

◆ ICMR1

volatile uint8_t r_i2c_regs_t::ICMR1

+0x02 Bus Mode Register 1 (HUM 39.2.3, p 2374).

Definition at line 81 of file ra8_i2c_regs.h.

Referenced by internal_i2c_apply_init_regs(), and ra8_i2c_set_clock().

◆ ICMR2

volatile uint8_t r_i2c_regs_t::ICMR2

+0x03 Bus Mode Register 2 (HUM 39.2.4, p 2375).

Definition at line 82 of file ra8_i2c_regs.h.

◆ ICMR3

volatile uint8_t r_i2c_regs_t::ICMR3

+0x04 Bus Mode Register 3 (HUM 39.2.5, p 2376).

Definition at line 83 of file ra8_i2c_regs.h.

Referenced by internal_i2c_drain_rx(), internal_i2c_set_nack(), ra8_i2c_peripheral_deinit(), and ra8_i2c_peripheral_init().

◆ ICSER

volatile uint8_t r_i2c_regs_t::ICSER

+0x06 Bus Status Enable (HUM 39.2.7, p 2380).

Definition at line 85 of file ra8_i2c_regs.h.

Referenced by ra8_i2c_peripheral_deinit(), and ra8_i2c_peripheral_init().

◆ ICSR1

volatile uint8_t r_i2c_regs_t::ICSR1

+0x08 Bus Status Register 1 (HUM 39.2.9, p 2382).

Definition at line 87 of file ra8_i2c_regs.h.

Referenced by ra8_i2c_peripheral_dispatch(), and ra8_i2c_peripheral_poll().

◆ ICSR2

volatile uint8_t r_i2c_regs_t::ICSR2

+0x09 Bus Status Register 2 (HUM 39.2.10, p 2384).

Definition at line 88 of file ra8_i2c_regs.h.

Referenced by internal_i2c_clear_status(), internal_i2c_drain_tx(), internal_i2c_send_address(), internal_i2c_stop_request(), internal_i2c_target_fill_tx(), internal_i2c_target_finish_tx(), internal_i2c_target_wait(), internal_i2c_wait_icsr2(), priv_ra8_i2c_internal_target_drain_rx(), ra8_i2c_clear_errors(), ra8_i2c_get_errors(), ra8_i2c_peripheral_dispatch(), ra8_i2c_peripheral_poll(), ra8_i2c_peripheral_receive(), ra8_i2c_read(), and ra8_i2c_scan().

◆ ICWUR

volatile uint8_t r_i2c_regs_t::ICWUR

+0x14 Wakeup Unit Register (HUM 39.2.11, p 2388).

Definition at line 99 of file ra8_i2c_regs.h.

◆ ICWUR2

volatile uint8_t r_i2c_regs_t::ICWUR2

+0x15 Wakeup Unit Register 2 (HUM 39.2.12, p 2389).

Definition at line 100 of file ra8_i2c_regs.h.

◆ SARL0

volatile uint8_t r_i2c_regs_t::SARL0

+0x0A Peripheral Address L0 (HUM 39.2.13, p 2390).

Definition at line 89 of file ra8_i2c_regs.h.

Referenced by internal_i2c_target_set_addr().

◆ SARL1

volatile uint8_t r_i2c_regs_t::SARL1

+0x0C Peripheral Address L1 (HUM 39.2.13, p 2390).

Definition at line 91 of file ra8_i2c_regs.h.

Referenced by internal_i2c_target_set_addr().

◆ SARL2

volatile uint8_t r_i2c_regs_t::SARL2

+0x0E Peripheral Address L2 (HUM 39.2.13, p 2390).

Definition at line 93 of file ra8_i2c_regs.h.

Referenced by internal_i2c_target_set_addr().

◆ SARU0

volatile uint8_t r_i2c_regs_t::SARU0

+0x0B Peripheral Address U0 (HUM 39.2.14, p 2391).

Definition at line 90 of file ra8_i2c_regs.h.

Referenced by internal_i2c_target_set_addr().

◆ SARU1

volatile uint8_t r_i2c_regs_t::SARU1

+0x0D Peripheral Address U1 (HUM 39.2.14, p 2391).

Definition at line 92 of file ra8_i2c_regs.h.

Referenced by internal_i2c_target_set_addr().

◆ SARU2

volatile uint8_t r_i2c_regs_t::SARU2

+0x0F Peripheral Address U2 (HUM 39.2.14, p 2391).

Definition at line 94 of file ra8_i2c_regs.h.

Referenced by internal_i2c_target_set_addr().

The documentation for this struct was generated from the following file: