ra8_i2c_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_i2c0_base_addr     = 0x4025E000UL, 
  k_ra8_i2c_channel_stride = 0x00000100UL, 
} ra8_i2c_addr_t;

typedef enum : uint16_t {
  k_ra8_i2c_channel_count    = 3U,  
  k_ra8_i2c_regs_block_bytes = 22U, 
} ra8_i2c_limits_t;

typedef struct {
  volatile uint8_t ICCR1;  
  volatile uint8_t ICCR2;  
  volatile uint8_t ICMR1;  
  volatile uint8_t ICMR2;  
  volatile uint8_t ICMR3;  
  volatile uint8_t ICFER;  
  volatile uint8_t ICSER;  
  volatile uint8_t ICIER;  
  volatile uint8_t ICSR1;  
  volatile uint8_t ICSR2;  
  volatile uint8_t SARL0;  
  volatile uint8_t SARU0;  
  volatile uint8_t SARL1;  
  volatile uint8_t SARU1;  
  volatile uint8_t SARL2;  
  volatile uint8_t SARU2;  
  volatile uint8_t ICBRL;  
  volatile uint8_t ICBRH;  
  volatile uint8_t ICDRT;  
  volatile uint8_t ICDRR;  
  volatile uint8_t ICWUR;  
  volatile uint8_t ICWUR2; 
} r_i2c_regs_t;
 
static_assert(sizeof(r_i2c_regs_t) == (size_t)k_ra8_i2c_regs_block_bytes,
              "RIIC register block must be 22 (0x16) bytes");
 
/* =============================================================================
 * Bit positions for the registers actually programmed by the polling-mode
 * IIC controller driver. Names mirror the HUM bit names -- HUM Ch 39.2,
 * p 2369..2394.
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_i2c_iccr1_sdai_pos   = 0U, 
  k_ra8_i2c_iccr1_scli_pos   = 1U, 
  k_ra8_i2c_iccr1_sdao_pos   = 2U, 
  k_ra8_i2c_iccr1_sclo_pos   = 3U, 
  k_ra8_i2c_iccr1_sowp_pos   = 4U, 
  k_ra8_i2c_iccr1_clo_pos    = 5U, 
  k_ra8_i2c_iccr1_iicrst_pos = 6U, 
  k_ra8_i2c_iccr1_ice_pos    = 7U, 
} ra8_i2c_iccr1_t;

typedef enum : uint8_t {
  k_ra8_i2c_iccr2_st_pos   = 1U, 
  k_ra8_i2c_iccr2_rs_pos   = 2U, 
  k_ra8_i2c_iccr2_sp_pos   = 3U, 
  k_ra8_i2c_iccr2_trs_pos  = 5U, 
  k_ra8_i2c_iccr2_mst_pos  = 6U, 
  k_ra8_i2c_iccr2_bbsy_pos = 7U, 
} ra8_i2c_iccr2_t;

typedef enum : uint8_t {
  k_ra8_i2c_icmr1_cks_pos  = 4U, 
  k_ra8_i2c_icmr1_mtwp_pos = 7U, 
} ra8_i2c_icmr1_t;

typedef enum : uint8_t {
  k_ra8_i2c_icmr3_ackbr_pos = 2U, 
  k_ra8_i2c_icmr3_ackbt_pos = 3U, 
  k_ra8_i2c_icmr3_ackwp_pos = 4U, 
  k_ra8_i2c_icmr3_rdrfs_pos = 5U, 
  k_ra8_i2c_icmr3_wait_pos  = 6U, 
  k_ra8_i2c_icmr3_smbs_pos  = 7U, 
} ra8_i2c_icmr3_t;

typedef enum : uint8_t {
  k_ra8_i2c_icfer_tmoe_pos  = 0U, 
  k_ra8_i2c_icfer_male_pos  = 1U, 
  k_ra8_i2c_icfer_nale_pos  = 2U, 
  k_ra8_i2c_icfer_sale_pos  = 3U, 
  k_ra8_i2c_icfer_nacke_pos = 4U, 
  k_ra8_i2c_icfer_nfe_pos   = 5U, 
  k_ra8_i2c_icfer_scle_pos  = 6U, 
  k_ra8_i2c_icfer_fmpe_pos  = 7U, 
} ra8_i2c_icfer_t;

typedef enum : uint8_t {
  k_ra8_i2c_icier_tmoie_pos = 0U, 
  k_ra8_i2c_icier_alie_pos  = 1U, 
  k_ra8_i2c_icier_stie_pos  = 2U, 
  k_ra8_i2c_icier_spie_pos  = 3U, 
  k_ra8_i2c_icier_nakie_pos = 4U, 
  k_ra8_i2c_icier_rie_pos   = 5U, 
  k_ra8_i2c_icier_teie_pos  = 6U, 
  k_ra8_i2c_icier_tie_pos   = 7U, 
} ra8_i2c_icier_t;

typedef enum : uint8_t {
  k_ra8_i2c_icsr2_tmof_pos  = 0U, 
  k_ra8_i2c_icsr2_al_pos    = 1U, 
  k_ra8_i2c_icsr2_start_pos = 2U, 
  k_ra8_i2c_icsr2_stop_pos  = 3U, 
  k_ra8_i2c_icsr2_nackf_pos = 4U, 
  k_ra8_i2c_icsr2_rdrf_pos  = 5U, 
  k_ra8_i2c_icsr2_tend_pos  = 6U, 
  k_ra8_i2c_icsr2_tdre_pos  = 7U, 
} ra8_i2c_icsr2_t;

typedef enum : uint8_t {
  k_ra8_i2c_icser_sar0e_pos = 0U, 
  k_ra8_i2c_icser_sar1e_pos = 1U, 
  k_ra8_i2c_icser_sar2e_pos = 2U, 
  k_ra8_i2c_icser_gcae_pos  = 3U, 
  k_ra8_i2c_icser_dide_pos  = 5U, 
  k_ra8_i2c_icser_hoae_pos  = 7U, 
} ra8_i2c_icser_t;

typedef enum : uint8_t {
  k_ra8_i2c_icsr1_aas0_pos = 0U, 
  k_ra8_i2c_icsr1_aas1_pos = 1U, 
  k_ra8_i2c_icsr1_aas2_pos = 2U, 
  k_ra8_i2c_icsr1_gca_pos  = 3U, 
  k_ra8_i2c_icsr1_did_pos  = 5U, 
  k_ra8_i2c_icsr1_hoa_pos  = 7U, 
} ra8_i2c_icsr1_t;

typedef enum : uint8_t {
  k_ra8_i2c_sarl_sva0_pos = 0U, 
  k_ra8_i2c_sarl_sva_pos  = 1U, 
} ra8_i2c_sarl_t;

typedef enum : uint8_t {
  k_ra8_i2c_saru_fs_pos  = 0U, 
  k_ra8_i2c_saru_sva_pos = 1U, 
} ra8_i2c_saru_t;
 
/* =============================================================================
 * Composite masks. Keeping masks as a typed enum (uint8_t) lets callers OR
 * them together without per-call shift expressions.
 * =============================================================================
 */

typedef enum : uint8_t {
  k_ra8_i2c_msk_iccr1_sowp   = (uint8_t)(1U << 4U), 
  k_ra8_i2c_msk_iccr1_iicrst = (uint8_t)(1U << 6U), 
  k_ra8_i2c_msk_iccr1_ice    = (uint8_t)(1U << 7U), 
  k_ra8_i2c_msk_iccr2_st     = (uint8_t)(1U << 1U), 
  k_ra8_i2c_msk_iccr2_rs     = (uint8_t)(1U << 2U), 
  k_ra8_i2c_msk_iccr2_sp     = (uint8_t)(1U << 3U), 
  k_ra8_i2c_msk_iccr2_trs    = (uint8_t)(1U << 5U), 
  k_ra8_i2c_msk_iccr2_mst    = (uint8_t)(1U << 6U), 
  k_ra8_i2c_msk_iccr2_bbsy   = (uint8_t)(1U << 7U), 
  k_ra8_i2c_msk_icmr3_ackbr  = (uint8_t)(1U << 2U), 
  k_ra8_i2c_msk_icmr3_ackbt  = (uint8_t)(1U << 3U), 
  k_ra8_i2c_msk_icmr3_ackwp  = (uint8_t)(1U << 4U), 
  k_ra8_i2c_msk_icmr3_wait   = (uint8_t)(1U << 6U), 
  k_ra8_i2c_msk_icfer_male   = (uint8_t)(1U << 1U), 
  k_ra8_i2c_msk_icfer_nacke  = (uint8_t)(1U << 4U), 
  k_ra8_i2c_msk_icfer_nfe    = (uint8_t)(1U << 5U), 
  k_ra8_i2c_msk_icfer_scle   = (uint8_t)(1U << 6U), 
  k_ra8_i2c_msk_icfer_fmpe   = (uint8_t)(1U << 7U), 
  k_ra8_i2c_msk_icsr2_al     = (uint8_t)(1U << 1U), 
  k_ra8_i2c_msk_icsr2_stop   = (uint8_t)(1U << 3U), 
  k_ra8_i2c_msk_icsr2_nackf  = (uint8_t)(1U << 4U), 
  k_ra8_i2c_msk_icsr2_rdrf   = (uint8_t)(1U << 5U), 
  k_ra8_i2c_msk_icsr2_tend   = (uint8_t)(1U << 6U), 
  k_ra8_i2c_msk_icsr2_tdre   = (uint8_t)(1U << 7U), 
  k_ra8_i2c_msk_icmr1_mtwp   = (uint8_t)(1U << 7U), 
} ra8_i2c_mask_t;

typedef enum : uint8_t {
  k_ra8_i2c_msk_icser_sar0e = (uint8_t)(1U << 0U), 
  k_ra8_i2c_msk_icser_sar1e = (uint8_t)(1U << 1U), 
  k_ra8_i2c_msk_icser_sar2e = (uint8_t)(1U << 2U), 
  k_ra8_i2c_msk_icser_gcae  = (uint8_t)(1U << 3U), 
  k_ra8_i2c_msk_icsr1_aas0  = (uint8_t)(1U << 0U), 
  k_ra8_i2c_msk_icsr1_aas1  = (uint8_t)(1U << 1U), 
  k_ra8_i2c_msk_icsr1_aas2  = (uint8_t)(1U << 2U), 
  k_ra8_i2c_msk_icsr1_gca   = (uint8_t)(1U << 3U), 
  k_ra8_i2c_msk_icsr1_match = (uint8_t)((1U << 0U) | (1U << 1U) | (1U << 2U) | (1U << 3U)),
} ra8_i2c_peripheral_mask_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_i2c_regs_t* ra8_i2c_regs(uint8_t channel)
{
  if ((uint16_t)channel >= (uint16_t)k_ra8_i2c_channel_count) {
    return nullptr;
  }
  const uintptr_t base =
    (uintptr_t)k_ra8_i2c0_base_addr + ((uintptr_t)channel * (uintptr_t)k_ra8_i2c_channel_stride);
  return (volatile r_i2c_regs_t*)base;
}
 
#ifdef __cplusplus
}
#endif