ra8_i2c_regs.h File Reference

I2C Bus Interface (IIC) register layout for the Renesas RA8D2. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"

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Data Structures
struct	r_i2c_regs_t
	Memory-mapped register block for one IIC channel. More...

Enumerations
enum	ra8_i2c_addr_t : uintptr_t {   k_ra8_i2c0_base_addr = 0x4025E000UL ,   k_ra8_i2c_channel_stride = 0x00000100UL }
	Hardware base addresses for the IIC channels. More...
enum	ra8_i2c_limits_t : uint16_t {   k_ra8_i2c_channel_count = 3U ,   k_ra8_i2c_regs_block_bytes = 22U }
	Channel-count limits. More...
enum	ra8_i2c_iccr1_t : uint8_t {   k_ra8_i2c_iccr1_sdai_pos = 0U ,   k_ra8_i2c_iccr1_scli_pos = 1U ,   k_ra8_i2c_iccr1_sdao_pos = 2U ,   k_ra8_i2c_iccr1_sclo_pos = 3U ,   k_ra8_i2c_iccr1_sowp_pos = 4U ,   k_ra8_i2c_iccr1_clo_pos = 5U ,   k_ra8_i2c_iccr1_iicrst_pos = 6U ,   k_ra8_i2c_iccr1_ice_pos = 7U }
	ICCR1 (Bus Control 1) field positions (HUM Ch 39.2.1, p 2369). More...
enum	ra8_i2c_iccr2_t : uint8_t {   k_ra8_i2c_iccr2_st_pos = 1U ,   k_ra8_i2c_iccr2_rs_pos = 2U ,   k_ra8_i2c_iccr2_sp_pos = 3U ,   k_ra8_i2c_iccr2_trs_pos = 5U ,   k_ra8_i2c_iccr2_mst_pos = 6U ,   k_ra8_i2c_iccr2_bbsy_pos = 7U }
	ICCR2 (Bus Control 2) field positions (HUM Ch 39.2.2, p 2371). More...
enum	ra8_i2c_icmr1_t : uint8_t {   k_ra8_i2c_icmr1_cks_pos = 4U ,   k_ra8_i2c_icmr1_mtwp_pos = 7U }
	ICMR1 (Bus Mode 1) field positions (HUM Ch 39.2.3, p 2374). More...
enum	ra8_i2c_icmr3_t : uint8_t {   k_ra8_i2c_icmr3_ackbr_pos = 2U ,   k_ra8_i2c_icmr3_ackbt_pos = 3U ,   k_ra8_i2c_icmr3_ackwp_pos = 4U ,   k_ra8_i2c_icmr3_rdrfs_pos = 5U ,   k_ra8_i2c_icmr3_wait_pos = 6U ,   k_ra8_i2c_icmr3_smbs_pos = 7U }
	ICMR3 (Bus Mode 3) field positions (HUM Ch 39.2.5, p 2376). More...
enum	ra8_i2c_icfer_t : uint8_t {   k_ra8_i2c_icfer_tmoe_pos = 0U ,   k_ra8_i2c_icfer_male_pos = 1U ,   k_ra8_i2c_icfer_nale_pos = 2U ,   k_ra8_i2c_icfer_sale_pos = 3U ,   k_ra8_i2c_icfer_nacke_pos = 4U ,   k_ra8_i2c_icfer_nfe_pos = 5U ,   k_ra8_i2c_icfer_scle_pos = 6U ,   k_ra8_i2c_icfer_fmpe_pos = 7U }
	ICFER (Bus Function Enable) field positions (HUM Ch 39.2.6, p 2378). More...
enum	ra8_i2c_icier_t : uint8_t {   k_ra8_i2c_icier_tmoie_pos = 0U ,   k_ra8_i2c_icier_alie_pos = 1U ,   k_ra8_i2c_icier_stie_pos = 2U ,   k_ra8_i2c_icier_spie_pos = 3U ,   k_ra8_i2c_icier_nakie_pos = 4U ,   k_ra8_i2c_icier_rie_pos = 5U ,   k_ra8_i2c_icier_teie_pos = 6U ,   k_ra8_i2c_icier_tie_pos = 7U }
	ICIER (Bus Interrupt Enable) field positions (HUM Ch 39.2.8, p 2381). More...
enum	ra8_i2c_icsr2_t : uint8_t {   k_ra8_i2c_icsr2_tmof_pos = 0U ,   k_ra8_i2c_icsr2_al_pos = 1U ,   k_ra8_i2c_icsr2_start_pos = 2U ,   k_ra8_i2c_icsr2_stop_pos = 3U ,   k_ra8_i2c_icsr2_nackf_pos = 4U ,   k_ra8_i2c_icsr2_rdrf_pos = 5U ,   k_ra8_i2c_icsr2_tend_pos = 6U ,   k_ra8_i2c_icsr2_tdre_pos = 7U }
	ICSR2 (Bus Status 2) field positions (HUM Ch 39.2.10, p 2384). More...
enum	ra8_i2c_icser_t : uint8_t {   k_ra8_i2c_icser_sar0e_pos = 0U ,   k_ra8_i2c_icser_sar1e_pos = 1U ,   k_ra8_i2c_icser_sar2e_pos = 2U ,   k_ra8_i2c_icser_gcae_pos = 3U ,   k_ra8_i2c_icser_dide_pos = 5U ,   k_ra8_i2c_icser_hoae_pos = 7U }
	ICSER (Bus Status Enable) field positions (HUM Ch 39.2.7, p 2380). More...
enum	ra8_i2c_icsr1_t : uint8_t {   k_ra8_i2c_icsr1_aas0_pos = 0U ,   k_ra8_i2c_icsr1_aas1_pos = 1U ,   k_ra8_i2c_icsr1_aas2_pos = 2U ,   k_ra8_i2c_icsr1_gca_pos = 3U ,   k_ra8_i2c_icsr1_did_pos = 5U ,   k_ra8_i2c_icsr1_hoa_pos = 7U }
	ICSR1 (Bus Status 1) field positions (HUM Ch 39.2.9, p 2382). More...
enum	ra8_i2c_sarl_t : uint8_t {   k_ra8_i2c_sarl_sva0_pos = 0U ,   k_ra8_i2c_sarl_sva_pos = 1U }
	SARLy (own-address lower) field positions (HUM Ch 39.2.13, p 2390). More...
enum	ra8_i2c_saru_t : uint8_t {   k_ra8_i2c_saru_fs_pos = 0U ,   k_ra8_i2c_saru_sva_pos = 1U }
	SARUy (own-address upper) field positions (HUM Ch 39.2.14, p 2391). More...
enum	ra8_i2c_mask_t : uint8_t {   k_ra8_i2c_msk_iccr1_sowp = (uint8_t)(1U << 4U) ,   k_ra8_i2c_msk_iccr1_iicrst = (uint8_t)(1U << 6U) ,   k_ra8_i2c_msk_iccr1_ice = (uint8_t)(1U << 7U) ,   k_ra8_i2c_msk_iccr2_st = (uint8_t)(1U << 1U) ,   k_ra8_i2c_msk_iccr2_rs = (uint8_t)(1U << 2U) ,   k_ra8_i2c_msk_iccr2_sp = (uint8_t)(1U << 3U) ,   k_ra8_i2c_msk_iccr2_trs = (uint8_t)(1U << 5U) ,   k_ra8_i2c_msk_iccr2_mst = (uint8_t)(1U << 6U) ,   k_ra8_i2c_msk_iccr2_bbsy = (uint8_t)(1U << 7U) ,   k_ra8_i2c_msk_icmr3_ackbr = (uint8_t)(1U << 2U) ,   k_ra8_i2c_msk_icmr3_ackbt = (uint8_t)(1U << 3U) ,   k_ra8_i2c_msk_icmr3_ackwp = (uint8_t)(1U << 4U) ,   k_ra8_i2c_msk_icmr3_wait = (uint8_t)(1U << 6U) ,   k_ra8_i2c_msk_icfer_male = (uint8_t)(1U << 1U) ,   k_ra8_i2c_msk_icfer_nacke = (uint8_t)(1U << 4U) ,   k_ra8_i2c_msk_icfer_nfe = (uint8_t)(1U << 5U) ,   k_ra8_i2c_msk_icfer_scle = (uint8_t)(1U << 6U) ,   k_ra8_i2c_msk_icfer_fmpe = (uint8_t)(1U << 7U) ,   k_ra8_i2c_msk_icsr2_al = (uint8_t)(1U << 1U) ,   k_ra8_i2c_msk_icsr2_stop = (uint8_t)(1U << 3U) ,   k_ra8_i2c_msk_icsr2_nackf = (uint8_t)(1U << 4U) ,   k_ra8_i2c_msk_icsr2_rdrf = (uint8_t)(1U << 5U) ,   k_ra8_i2c_msk_icsr2_tend = (uint8_t)(1U << 6U) ,   k_ra8_i2c_msk_icsr2_tdre = (uint8_t)(1U << 7U) ,   k_ra8_i2c_msk_icmr1_mtwp = (uint8_t)(1U << 7U) }
	Composite bit masks used by the polling driver (HUM Ch 39.2). More...
enum	ra8_i2c_peripheral_mask_t : uint8_t {   k_ra8_i2c_msk_icser_sar0e = (uint8_t)(1U << 0U) ,   k_ra8_i2c_msk_icser_sar1e = (uint8_t)(1U << 1U) ,   k_ra8_i2c_msk_icser_sar2e = (uint8_t)(1U << 2U) ,   k_ra8_i2c_msk_icser_gcae = (uint8_t)(1U << 3U) ,   k_ra8_i2c_msk_icsr1_aas0 = (uint8_t)(1U << 0U) ,   k_ra8_i2c_msk_icsr1_aas1 = (uint8_t)(1U << 1U) ,   k_ra8_i2c_msk_icsr1_aas2 = (uint8_t)(1U << 2U) ,   k_ra8_i2c_msk_icsr1_gca = (uint8_t)(1U << 3U) ,   k_ra8_i2c_msk_icsr1_match = (uint8_t)((1U << 0U) | (1U << 1U) | (1U << 2U) | (1U << 3U)) }
	Composite masks for the target (peripheral) role (HUM Ch 39.2). More...

Functions
static volatile r_i2c_regs_t *	ra8_i2c_regs (uint8_t channel)
	Get a pointer to the IIC channel channel register block.

Detailed Description

I2C Bus Interface (IIC) register layout for the Renesas RA8D2.

Tag

[Ring 3 / HAL] {World: NS}

Three RIIC channels (IIC0/IIC1/IIC2) at base 0x4025_E000 + 0x0100 * n – this is the classic Renesas RIIC register block (ICCR1, ICCR2, ICMR1..3, ICFER, ICSER, ICIER, ICSR1/2, SARLy/SARUy, ICBRL/ICBRH, ICDRT, ICDRR). It is the peripheral the RA8D2 HUM calls "I2C Bus Interface (IIC)" and that FSP drives with r_iic_master – distinct from the I3C unified IP (ra8_i3c / ra8_i3c_i2c) at 0x4035_F000.

This header is hand-derived from the RA8D2 Hardware User's Manual Chapter 39 "I2C Bus Interface (IIC)" register descriptions (HUM Ch 39.2, p 2369-2394). Every RIIC register is a single byte; the registers are laid out contiguously from offset 0x00.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file ra8_i2c_regs.h.

Enumeration Type Documentation

ra8_i2c_addr_t

enum ra8_i2c_addr_t : uintptr_t

Hardware base addresses for the IIC channels.

Per HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1" p 2369 the channel base is IICn = 0x4025_E000 + 0x0100 * n (n = 0..2). The HAL only ever programmes the S/non-aliased view; the NS alias lives at 0x5025_E000 + 0x0100 * n.

Invariant

k_ra8_i2c_channel_stride separates consecutive channels.

Enumerator
k_ra8_i2c0_base_addr	HUM Ch 39.2.1, p 2369.
k_ra8_i2c_channel_stride	HUM Ch 39.2.1, p 2369.

Definition at line 51 of file ra8_i2c_regs.h.

ra8_i2c_iccr1_t

enum ra8_i2c_iccr1_t : uint8_t

ICCR1 (Bus Control 1) field positions (HUM Ch 39.2.1, p 2369).

Enumerator
k_ra8_i2c_iccr1_sdai_pos	SDA line monitor (R).
k_ra8_i2c_iccr1_scli_pos	SCL line monitor (R).
k_ra8_i2c_iccr1_sdao_pos	SDA output control/monitor.
k_ra8_i2c_iccr1_sclo_pos	SCL output control/monitor.
k_ra8_i2c_iccr1_sowp_pos	SCLO/SDAO write protect.
k_ra8_i2c_iccr1_clo_pos	Extra SCL clock cycle output.
k_ra8_i2c_iccr1_iicrst_pos	I2C internal reset.
k_ra8_i2c_iccr1_ice_pos	I2C interface enable.

Definition at line 117 of file ra8_i2c_regs.h.

ra8_i2c_iccr2_t

enum ra8_i2c_iccr2_t : uint8_t

ICCR2 (Bus Control 2) field positions (HUM Ch 39.2.2, p 2371).

Enumerator
k_ra8_i2c_iccr2_st_pos	Start condition issuance request.
k_ra8_i2c_iccr2_rs_pos	Restart condition issuance request.
k_ra8_i2c_iccr2_sp_pos	Stop condition issuance request.
k_ra8_i2c_iccr2_trs_pos	Transmit/receive mode.
k_ra8_i2c_iccr2_mst_pos	Controller/peripheral mode.
k_ra8_i2c_iccr2_bbsy_pos	Bus busy detection flag (R).

Definition at line 132 of file ra8_i2c_regs.h.

ra8_i2c_icfer_t

enum ra8_i2c_icfer_t : uint8_t

ICFER (Bus Function Enable) field positions (HUM Ch 39.2.6, p 2378).

Enumerator
k_ra8_i2c_icfer_tmoe_pos	Timeout function enable.
k_ra8_i2c_icfer_male_pos	Controller arbitration-lost detect enable.
k_ra8_i2c_icfer_nale_pos	NACK transmit arbitration-lost enable.
k_ra8_i2c_icfer_sale_pos	Peripheral arbitration-lost enable.
k_ra8_i2c_icfer_nacke_pos	NACK reception transfer suspension enable.
k_ra8_i2c_icfer_nfe_pos	Digital noise filter enable.
k_ra8_i2c_icfer_scle_pos	SCL synchronous circuit enable.
k_ra8_i2c_icfer_fmpe_pos	Fast-mode plus enable.

Definition at line 167 of file ra8_i2c_regs.h.

ra8_i2c_icier_t

enum ra8_i2c_icier_t : uint8_t

ICIER (Bus Interrupt Enable) field positions (HUM Ch 39.2.8, p 2381).

Enumerator
k_ra8_i2c_icier_tmoie_pos	Timeout interrupt enable.
k_ra8_i2c_icier_alie_pos	Arbitration-lost interrupt enable.
k_ra8_i2c_icier_stie_pos	Start condition interrupt enable.
k_ra8_i2c_icier_spie_pos	Stop condition interrupt enable.
k_ra8_i2c_icier_nakie_pos	NACK reception interrupt enable.
k_ra8_i2c_icier_rie_pos	Receive data full interrupt enable.
k_ra8_i2c_icier_teie_pos	Transmit end interrupt enable.
k_ra8_i2c_icier_tie_pos	Transmit data empty interrupt enable.

Definition at line 182 of file ra8_i2c_regs.h.

ra8_i2c_icmr1_t

enum ra8_i2c_icmr1_t : uint8_t

ICMR1 (Bus Mode 1) field positions (HUM Ch 39.2.3, p 2374).

Enumerator
k_ra8_i2c_icmr1_cks_pos	Internal reference clock select [6:4].
k_ra8_i2c_icmr1_mtwp_pos	MST/TRS write protect.

Definition at line 145 of file ra8_i2c_regs.h.

ra8_i2c_icmr3_t

enum ra8_i2c_icmr3_t : uint8_t

ICMR3 (Bus Mode 3) field positions (HUM Ch 39.2.5, p 2376).

Enumerator
k_ra8_i2c_icmr3_ackbr_pos	Receive acknowledge (R).
k_ra8_i2c_icmr3_ackbt_pos	Transmit acknowledge.
k_ra8_i2c_icmr3_ackwp_pos	ACKBT write protect.
k_ra8_i2c_icmr3_rdrfs_pos	RDRF flag set timing select.
k_ra8_i2c_icmr3_wait_pos	Wait between 9th and 1st clock.
k_ra8_i2c_icmr3_smbs_pos	SMBus/I2C select.

Definition at line 154 of file ra8_i2c_regs.h.

ra8_i2c_icser_t

enum ra8_i2c_icser_t : uint8_t

ICSER (Bus Status Enable) field positions (HUM Ch 39.2.7, p 2380).

Own-address-match enables used by the target (peripheral) role. Each SARyE bit arms the matching SARLy / SARUy own-address slot, and GCAE arms the I2C general-call address (0000 000b + 0[W]). Bits 4 and 6 are reserved. Each SARyE bit is this driver's inclusive "own-address slot y" match-enable.

Enumerator
k_ra8_i2c_icser_sar0e_pos	Own-address slot 0 match enable.
k_ra8_i2c_icser_sar1e_pos	Own-address slot 1 match enable.
k_ra8_i2c_icser_sar2e_pos	Own-address slot 2 match enable.
k_ra8_i2c_icser_gcae_pos	General-call address enable.
k_ra8_i2c_icser_dide_pos	Device-ID address detect enable.
k_ra8_i2c_icser_hoae_pos	Host-address enable.

Definition at line 219 of file ra8_i2c_regs.h.

ra8_i2c_icsr1_t

enum ra8_i2c_icsr1_t : uint8_t

ICSR1 (Bus Status 1) field positions (HUM Ch 39.2.9, p 2382).

Own-address detection flags. After a controller issues a START and an address that matches an enabled own-address slot, the hardware raises the matching AASy flag (or GCA for the general-call address) on the rising edge of the ninth SCL clock. These flags are cleared automatically when the bus STOP condition is detected.

Enumerator
k_ra8_i2c_icsr1_aas0_pos	Own-address slot 0 detected.
k_ra8_i2c_icsr1_aas1_pos	Own-address slot 1 detected.
k_ra8_i2c_icsr1_aas2_pos	Own-address slot 2 detected.
k_ra8_i2c_icsr1_gca_pos	General-call address detected.
k_ra8_i2c_icsr1_did_pos	Device-ID address detected.
k_ra8_i2c_icsr1_hoa_pos	Host address detected.

Definition at line 239 of file ra8_i2c_regs.h.

ra8_i2c_icsr2_t

enum ra8_i2c_icsr2_t : uint8_t

ICSR2 (Bus Status 2) field positions (HUM Ch 39.2.10, p 2384).

Enumerator
k_ra8_i2c_icsr2_tmof_pos	Timeout detection flag.
k_ra8_i2c_icsr2_al_pos	Arbitration-lost flag.
k_ra8_i2c_icsr2_start_pos	Start condition detection flag.
k_ra8_i2c_icsr2_stop_pos	Stop condition detection flag.
k_ra8_i2c_icsr2_nackf_pos	NACK detection flag.
k_ra8_i2c_icsr2_rdrf_pos	Receive data full flag.
k_ra8_i2c_icsr2_tend_pos	Transmit end flag.
k_ra8_i2c_icsr2_tdre_pos	Transmit data empty flag.

Definition at line 197 of file ra8_i2c_regs.h.

ra8_i2c_limits_t

enum ra8_i2c_limits_t : uint16_t

Channel-count limits.

Enumerator
k_ra8_i2c_channel_count	HUM Ch 39.1, p 2367 (3 channels).
k_ra8_i2c_regs_block_bytes	sizeof(r_i2c_regs_t): 0x00..0x15.

Definition at line 60 of file ra8_i2c_regs.h.

ra8_i2c_mask_t

enum ra8_i2c_mask_t : uint8_t

Composite bit masks used by the polling driver (HUM Ch 39.2).

Enumerator
k_ra8_i2c_msk_iccr1_sowp	HUM 39.2.1 ICCR1.SOWP, p 2369.
k_ra8_i2c_msk_iccr1_iicrst	HUM 39.2.1 ICCR1.IICRST, p 2369.
k_ra8_i2c_msk_iccr1_ice	HUM 39.2.1 ICCR1.ICE, p 2369.
k_ra8_i2c_msk_iccr2_st	HUM 39.2.2 ICCR2.ST, p 2371.
k_ra8_i2c_msk_iccr2_rs	HUM 39.2.2 ICCR2.RS, p 2371.
k_ra8_i2c_msk_iccr2_sp	HUM 39.2.2 ICCR2.SP, p 2371.
k_ra8_i2c_msk_iccr2_trs	HUM 39.2.2 ICCR2.TRS, p 2371.
k_ra8_i2c_msk_iccr2_mst	HUM 39.2.2 ICCR2.MST, p 2371.
k_ra8_i2c_msk_iccr2_bbsy	HUM 39.2.2 ICCR2.BBSY, p 2371.
k_ra8_i2c_msk_icmr3_ackbr	HUM 39.2.5 ICMR3.ACKBR, p 2376.
k_ra8_i2c_msk_icmr3_ackbt	HUM 39.2.5 ICMR3.ACKBT, p 2376.
k_ra8_i2c_msk_icmr3_ackwp	HUM 39.2.5 ICMR3.ACKWP, p 2376.
k_ra8_i2c_msk_icmr3_wait	HUM 39.2.5 ICMR3.WAIT, p 2376.
k_ra8_i2c_msk_icfer_male	HUM 39.2.6 ICFER.MALE, p 2378.
k_ra8_i2c_msk_icfer_nacke	HUM 39.2.6 ICFER.NACKE, p 2378.
k_ra8_i2c_msk_icfer_nfe	HUM 39.2.6 ICFER.NFE, p 2378.
k_ra8_i2c_msk_icfer_scle	HUM 39.2.6 ICFER.SCLE, p 2378.
k_ra8_i2c_msk_icfer_fmpe	HUM 39.2.6 ICFER.FMPE, p 2378.
k_ra8_i2c_msk_icsr2_al	HUM 39.2.10 ICSR2.AL, p 2384.
k_ra8_i2c_msk_icsr2_stop	HUM 39.2.10 ICSR2.STOP, p 2384.
k_ra8_i2c_msk_icsr2_nackf	HUM 39.2.10 ICSR2.NACKF, p 2384.
k_ra8_i2c_msk_icsr2_rdrf	HUM 39.2.10 ICSR2.RDRF, p 2384.
k_ra8_i2c_msk_icsr2_tend	HUM 39.2.10 ICSR2.TEND, p 2384.
k_ra8_i2c_msk_icsr2_tdre	HUM 39.2.10 ICSR2.TDRE, p 2384.
k_ra8_i2c_msk_icmr1_mtwp	HUM 39.2.3 ICMR1.MTWP, p 2374.

Definition at line 286 of file ra8_i2c_regs.h.

ra8_i2c_peripheral_mask_t

enum ra8_i2c_peripheral_mask_t : uint8_t

Composite masks for the target (peripheral) role (HUM Ch 39.2).

Own-address enable bits (ICSER), own-address detection flags (ICSR1) and the union of all match flags used to decide that the controller addressed this device. Kept separate from ra8_i2c_mask_t so the controller-only transfer plane is unaffected.

Enumerator
k_ra8_i2c_msk_icser_sar0e	HUM 39.2.7 ICSER.SAR0E, p 2380.
k_ra8_i2c_msk_icser_sar1e	HUM 39.2.7 ICSER.SAR1E, p 2380.
k_ra8_i2c_msk_icser_sar2e	HUM 39.2.7 ICSER.SAR2E, p 2380.
k_ra8_i2c_msk_icser_gcae	HUM 39.2.7 ICSER.GCAE, p 2380.
k_ra8_i2c_msk_icsr1_aas0	HUM 39.2.9 ICSR1.AAS0, p 2382.
k_ra8_i2c_msk_icsr1_aas1	HUM 39.2.9 ICSR1.AAS1, p 2382.
k_ra8_i2c_msk_icsr1_aas2	HUM 39.2.9 ICSR1.AAS2, p 2382.
k_ra8_i2c_msk_icsr1_gca	HUM 39.2.9 ICSR1.GCA, p 2382.
k_ra8_i2c_msk_icsr1_match	Union AAS0|AAS1|AAS2|GCA: any own-address/general-call match.

Definition at line 324 of file ra8_i2c_regs.h.

ra8_i2c_sarl_t

enum ra8_i2c_sarl_t : uint8_t

SARLy (own-address lower) field positions (HUM Ch 39.2.13, p 2390).

In 7-bit format (SARUy.FS = 0) the SVA[6:0] field at bit 1 holds the whole 7-bit own address, so a 7-bit address is written left-shifted by one. SVA0 at bit 0 is the 10-bit LSB and is ignored in 7-bit format.

Enumerator
k_ra8_i2c_sarl_sva0_pos	10-bit own-address LSB (SVA0).
k_ra8_i2c_sarl_sva_pos	7-bit own address / 10-bit low SVA[6:0].

Definition at line 257 of file ra8_i2c_regs.h.

ra8_i2c_saru_t

enum ra8_i2c_saru_t : uint8_t

SARUy (own-address upper) field positions (HUM Ch 39.2.14, p 2391).

FS selects 7-bit (0) or 10-bit (1) own-address format; SVA[1:0] at bit 1 holds the two upper bits of a 10-bit own address. This polling-mode target driver only programmes the 7-bit format, so SARUy is written as 0.

Enumerator
k_ra8_i2c_saru_fs_pos	7-bit (0) / 10-bit (1) format select.
k_ra8_i2c_saru_sva_pos	10-bit own-address upper SVA[1:0].

Definition at line 271 of file ra8_i2c_regs.h.

Function Documentation

ra8_i2c_regs()

volatile r_i2c_regs_t * ra8_i2c_regs ( uint8_t channel )

inlinestatic

Get a pointer to the IIC channel channel register block.

Parameters

[in]

channel

Channel index. 0, 1 or 2 on the RA8D2.

Returns

volatile r_i2c_regs_t* Pointer to channel registers, or nullptr when channel is out of range.

Precondition

ra8_mstp_enable(k_ra8_mstp_iicN) has been called for the channel.

Postcondition

Returned pointer is nullptr or aliases k_ra8_i2c0_base_addr + channel * k_ra8_i2c_channel_stride.

Note

Inline – expands at the call site so the compiler can fold the channel-bounds check when called with a literal channel index.

See also

HUM Ch 39.2.1 "ICCR1 : I2C Bus Control Register 1", p 2369.

Since

0.1.0

Definition at line 356 of file ra8_i2c_regs.h.

References k_ra8_i2c0_base_addr, k_ra8_i2c_channel_count, and k_ra8_i2c_channel_stride.

Referenced by ra8_i2c_clear_errors(), ra8_i2c_deinit(), ra8_i2c_get_errors(), ra8_i2c_init(), ra8_i2c_peripheral_deinit(), ra8_i2c_peripheral_dispatch(), ra8_i2c_peripheral_init(), ra8_i2c_peripheral_poll(), ra8_i2c_peripheral_receive(), ra8_i2c_peripheral_transmit(), ra8_i2c_read(), ra8_i2c_scan(), ra8_i2c_set_clock(), ra8_i2c_transfer(), and ra8_i2c_write().