I3C Bus Interface register layout for the Renesas RA8D2. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_i3c_regs.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	r_i3c_regs_t
	Partial RA8D2 I3C0 register window. More...

Enumerations
enum	ra8_i3c_addr_t : uintptr_t { k_ra8_i3c0_base_addr = 0x4035F000UL , k_ra8_i3c1_base_addr = 0x4035F100UL , k_ra8_i3c_base_addr = k_ra8_i3c0_base_addr }
	I3C peripheral base addresses. More...
enum	ra8_i3c_limits_t : uint8_t { k_ra8_i3c_instance_count = 2U , k_ra8_i3c_pad_after_prts = 3U , k_ra8_i3c_pad_after_msdvad = 1U , k_ra8_i3c_pad_after_prsst = 2U , k_ra8_i3c_pad_after_instfc = 1U , k_ra8_i3c_pad_after_dvct = 4U , k_ra8_i3c_pad_after_ibinctl = 1U , k_ra8_i3c_pad_after_svctl = 2U , k_ra8_i3c_pad_after_tmoctl = 1U , k_ra8_i3c_pad_after_wuctl = 1U , k_ra8_i3c_pad_after_scstr = 2U , k_ra8_i3c_pad_after_scstlctl = 37U , k_ra8_i3c_pad_after_ntdtbp0 = 8U , k_ra8_i3c_pad_after_nrsqp = 23U }
	Reserved-padding word counts for r_i3c_regs_t. More...
enum	ra8_i3c_bctl_bits_t : uint32_t { k_ra8_i3c_bctl_incba_mask = 0x00000001UL , k_ra8_i3c_bctl_bmds_mask = 0x00000080UL , k_ra8_i3c_bctl_hjackctl_mask = 0x00000100UL , k_ra8_i3c_bctl_slve_mask = 0x00010000UL , k_ra8_i3c_bctl_abt_mask = 0x20000000UL , k_ra8_i3c_bctl_rsm_mask = 0x40000000UL , k_ra8_i3c_bctl_buse_mask = 0x80000000UL }
	BCTL register bit positions / masks. More...
enum	ra8_i3c_nsdvad_bits_t : uint32_t { k_ra8_i3c_nsdvad_sdyad_shift = 16U , k_ra8_i3c_nsdvad_sdyad_mask = 0x007F0000UL , k_ra8_i3c_nsdvad_sdyadv_mask = 0x80000000UL }
	NSDVAD (Peripheral Device Address Register) bit positions / masks. More...
enum	ra8_i3c_ntibivctl_bits_t : uint32_t { k_ra8_i3c_ntibivctl_vlcnt_mask = 0x000000FFUL , k_ra8_i3c_ntibivctl_vlcnt_shift = 0U }
	NTIBIVCTL (IBI Valid Control) field positions. More...
enum	ra8_i3c_cmd_hdr_mode_t : uint32_t { k_ra8_i3c_cmd_hdr_mode_sdr = 0UL , k_ra8_i3c_cmd_hdr_mode_ddr = 1UL , k_ra8_i3c_cmd_hdr_mode_ts = 2UL , k_ra8_i3c_cmd_hdr_mode_mask = 0x3UL }
	NCMDQP "transfer mode" attribute values for HDR transactions. More...
enum	ra8_i3c_msdvad_bits_t : uint32_t { k_ra8_i3c_msdvad_mdyad_shift = 16U , k_ra8_i3c_msdvad_mdyad_mask = 0x007F0000UL , k_ra8_i3c_msdvad_mdyadv_mask = 0x80000000UL , k_ra8_i3c_msdvad_addr_max = 0x7FUL }
	MSDVAD register bit positions / masks. More...
enum	ra8_i3c_rstctl_bits_t : uint32_t { k_ra8_i3c_rstctl_ri3crst_mask = 0x00000001UL , k_ra8_i3c_rstctl_cmdqrst_mask = 0x00000002UL , k_ra8_i3c_rstctl_rspqrst_mask = 0x00000004UL , k_ra8_i3c_rstctl_tdbrst_mask = 0x00000008UL , k_ra8_i3c_rstctl_rdbrst_mask = 0x00000010UL , k_ra8_i3c_rstctl_ibiqrst_mask = 0x00000020UL , k_ra8_i3c_rstctl_rsqrst_mask = 0x00000040UL , k_ra8_i3c_rstctl_intlrst_mask = 0x00010000UL , k_ra8_i3c_rstctl_fifo_mask }
	RSTCTL register bit positions / masks. More...
enum	ra8_i3c_inst_bits_t : uint32_t { k_ra8_i3c_inst_inef_mask = 0x00000400UL }
	INST/INSTE/INIE bit positions. More...
enum	ra8_i3c_ccc_opcode_t : uint8_t { k_ra8_i3c_ccc_b_enec = 0x00U , k_ra8_i3c_ccc_b_disec = 0x01U , k_ra8_i3c_ccc_b_entas0 = 0x02U , k_ra8_i3c_ccc_b_entas1 = 0x03U , k_ra8_i3c_ccc_b_entas2 = 0x04U , k_ra8_i3c_ccc_b_entas3 = 0x05U , k_ra8_i3c_ccc_b_rstdaa = 0x06U , k_ra8_i3c_ccc_b_entdaa = 0x07U , k_ra8_i3c_ccc_b_rstact = 0x2AU , k_ra8_i3c_ccc_d_enec = 0x80U , k_ra8_i3c_ccc_d_disec = 0x81U , k_ra8_i3c_ccc_d_entas0 = 0x82U , k_ra8_i3c_ccc_d_entas1 = 0x83U , k_ra8_i3c_ccc_d_entas2 = 0x84U , k_ra8_i3c_ccc_d_entas3 = 0x85U , k_ra8_i3c_ccc_d_setdasa = 0x87U , k_ra8_i3c_ccc_d_getmwl = 0x8BU , k_ra8_i3c_ccc_d_getmrl = 0x8CU , k_ra8_i3c_ccc_d_getpid = 0x8DU , k_ra8_i3c_ccc_d_getbcr = 0x8EU , k_ra8_i3c_ccc_d_getdcr = 0x8FU , k_ra8_i3c_ccc_d_getstatus = 0x90U , k_ra8_i3c_ccc_d_getxtime = 0x99U , k_ra8_i3c_ccc_d_rstact = 0x9AU , k_ra8_i3c_ccc_direct_mask = 0x80U }
	MIPI I3C v1.0 Common Command Code (CCC) opcodes. More...
enum	ra8_i3c_cmd_desc_bits_t : uint32_t { k_ra8_i3c_cmd_attr_shift = 0U , k_ra8_i3c_cmd_attr_xfer = 0U , k_ra8_i3c_cmd_attr_immed = 1U , k_ra8_i3c_cmd_attr_addr_assgn = 2U , k_ra8_i3c_cmd_tid_shift = 3U , k_ra8_i3c_cmd_code_shift = 7U , k_ra8_i3c_cmd_dev_index_shift = 16U , k_ra8_i3c_cmd_cp_shift = 15U , k_ra8_i3c_cmd_xfer_mode_shift = 26U , k_ra8_i3c_cmd_addr_count_shift = 26U , k_ra8_i3c_cmd_rnw_shift = 29U , k_ra8_i3c_cmd_roc_shift = 30U , k_ra8_i3c_cmd_toc_shift = 31U , k_ra8_i3c_cmd_immed_bytes_shift = 23U , k_ra8_i3c_cmd_xfer_length_shift = 16U , k_ra8_i3c_cmd_xfer_length_max = 0xFFFFUL }
	NCMDQP command-descriptor field positions (FSP I3C_CMD_DESC_*). More...
enum	ra8_i3c_ntst_bits_t : uint32_t { k_ra8_i3c_ntst_tdbef0_mask = 0x00000001UL , k_ra8_i3c_ntst_rdbff0_mask = 0x00000002UL , k_ra8_i3c_ntst_ibiqeff_mask = 0x00000004UL , k_ra8_i3c_ntst_cmdqef_mask = 0x00000008UL , k_ra8_i3c_ntst_rspqff_mask = 0x00000010UL , k_ra8_i3c_ntst_rsqff_mask = 0x00100000UL }
	NTST (Normal Transfer Status) flag positions. More...
enum	ra8_i3c_ibi_status_bits_t : uint32_t { k_ra8_i3c_ibi_status_length_shift = 0U , k_ra8_i3c_ibi_status_length_mask = 0x000000FFUL , k_ra8_i3c_ibi_status_id_shift = 8U , k_ra8_i3c_ibi_status_id_mask = 0x0000FF00UL , k_ra8_i3c_ibi_status_last_shift = 24U , k_ra8_i3c_ibi_status_ibi_st_mask = 0x80000000UL }
	IBI status descriptor field positions (FSP I3C_IBI_STATUS_DESC_*). More...
enum	ra8_i3c_misc_t : uint32_t { k_ra8_i3c_max_targets = 8U , k_ra8_i3c_pid_bytes = 6U , k_ra8_i3c_setdasa_payload_bytes = 1U , k_ra8_i3c_immediate_max_bytes = 4U , k_ra8_i3c_addr_mask = 0x7FU }
	Miscellaneous protocol limits. More...
enum	ra8_i3c_byte_t : uint32_t { k_ra8_i3c_byte_mask = 0xFFU , k_ra8_i3c_byte_shift = 8U , k_ra8_i3c_shift_b1 = 8U , k_ra8_i3c_shift_b2 = 16U , k_ra8_i3c_shift_b3 = 24U , k_ra8_i3c_addr_shift_in_ibi_id = 1U , k_ra8_i3c_word_size = 4U }
	Byte-pack helpers used to assemble / disassemble 32-bit FIFO words. More...
enum	ra8_i3c_offset_t : uint16_t { k_ra8_i3c_off_bctl = 0x014U , k_ra8_i3c_off_msdvad = 0x018U , k_ra8_i3c_off_rstctl = 0x020U , k_ra8_i3c_off_inst = 0x030U , k_ra8_i3c_off_dvct = 0x044U , k_ra8_i3c_off_ibinctl = 0x058U , k_ra8_i3c_off_bfctl = 0x060U , k_ra8_i3c_off_refckctl = 0x070U , k_ra8_i3c_off_ackctl = 0x0A0U , k_ra8_i3c_off_scstlctl = 0x0B0U , k_ra8_i3c_off_ncmdqp = 0x150U , k_ra8_i3c_off_nrspqp = 0x154U , k_ra8_i3c_off_ntdtbp0 = 0x158U , k_ra8_i3c_off_nibiqp = 0x17CU , k_ra8_i3c_off_nrsqp = 0x180U , k_ra8_i3c_off_ntst = 0x1E0U }
	FSP-canonical byte offsets used by the layout asserts below. More...

Functions
static volatile r_i3c_regs_t *	ra8_i3c (void)
	Get pointer to I3C0.

Detailed Description

I3C Bus Interface register layout for the Renesas RA8D2.

Two I3C instances are available on the RA8D2 (R_I3C0 at 0x4035F000 and R_I3C1 at 0x4035F100); this driver only exposes the first instance through ra8_i3c(). Layout is derived directly from the FSP CMSIS device header R7KA8D2KF_core0.h (R_I3C0_Type) and matches the field map in HUM Ch 40 "I3C Bus Interface (I3C)" pp 2445-2701.

Coverage spans the bring-up registers (PRTS, CECTL, BCTL, MSDVAD, RSTCTL, PRSST), the internal-error interrupt block (INST, INSTE, INIE, INSTFC), the IBI / arbitration controls (IBINCTL, BFCTL, SVCTL), the timing-and-rate group (REFCKCTL, STDBR, EXTBR, BFRECDT, BAVLCDT, BIDLCDT), the line-control

bus-status block (OUTCTL, INCTL, TMOCTL, WUCTL, ACKCTL, SCSTRCTL, SCSTLCTL), the FIFO port group used by the CCC engine (NCMDQP, NRSPQP, NTDTBP0, NIBIQP, NRSQP), and the Normal Transfer Status register (NTST). Members beyond NTST (HCMDQP, HRSPQP, HTDTBP, NQTHCTL, NTBTHCTL0, NRQTHCTL, HQTHCTL, HTBTHCTL, BST, BSTE, BIE, BSTFC, NTSTE, NTIE, HTST, BCST, SVST, DATBASn ...) are intentionally omitted because no driver code touches them yet – they land with the first HDR-DDR / peripheral-mode / sync-timing consumer.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_i3c_regs.h.

Enumeration Type Documentation

◆ ra8_i3c_addr_t

enum ra8_i3c_addr_t : uintptr_t

I3C peripheral base addresses.

Both instances share the identical R_I3C0_Type register layout, so the same struct overlay can describe either base.

Enumerator
k_ra8_i3c0_base_addr	I3C0 peripheral base.
k_ra8_i3c1_base_addr	I3C1 peripheral base.
k_ra8_i3c_base_addr	RA8 I3C base address.

Definition at line 52 of file ra8_i3c_regs.h.

◆ ra8_i3c_bctl_bits_t

enum ra8_i3c_bctl_bits_t : uint32_t

BCTL register bit positions / masks.

Enumerator
k_ra8_i3c_bctl_incba_mask	INCBA bit 0.
k_ra8_i3c_bctl_bmds_mask	BMDS bit 7.
k_ra8_i3c_bctl_hjackctl_mask	HJACKCTL bit 8.
k_ra8_i3c_bctl_slve_mask	SLVE bit 16 (peripheral-mode enable).
k_ra8_i3c_bctl_abt_mask	ABT bit 29.
k_ra8_i3c_bctl_rsm_mask	RSM bit 30.
k_ra8_i3c_bctl_buse_mask	BUSE bit 31.

Definition at line 190 of file ra8_i3c_regs.h.

◆ ra8_i3c_byte_t

enum ra8_i3c_byte_t : uint32_t

Byte-pack helpers used to assemble / disassemble 32-bit FIFO words.

Enumerator
k_ra8_i3c_byte_mask	Mask covering one byte.
k_ra8_i3c_byte_shift	Bits per byte.
k_ra8_i3c_shift_b1	Shift for byte 1 in a word.
k_ra8_i3c_shift_b2	Shift for byte 2 in a word.
k_ra8_i3c_shift_b3	Shift for byte 3 in a word.
k_ra8_i3c_addr_shift_in_ibi_id	IBI ID = (addr << 1) \| RnW.
k_ra8_i3c_word_size	Bytes per FIFO word.

Definition at line 402 of file ra8_i3c_regs.h.

◆ ra8_i3c_ccc_opcode_t

enum ra8_i3c_ccc_opcode_t : uint8_t

MIPI I3C v1.0 Common Command Code (CCC) opcodes.

Broadcast CCCs occupy 0x00..0x7F and are addressed to 0x7E (the I3C broadcast address). Direct CCCs occupy 0x80..0xFE and target a specific dynamic address after the CCC is issued. See HUM Ch 40 "I3C Bus Interface (I3C)" pp 2445-2701 and the MIPI I3C specification "Common Command Codes" table.

Enumerator
k_ra8_i3c_ccc_b_enec	Broadcast Enable Peripheral Events.
k_ra8_i3c_ccc_b_disec	Broadcast Disable Peripheral Events.
k_ra8_i3c_ccc_b_entas0	Broadcast Enter Activity State 0.
k_ra8_i3c_ccc_b_entas1	Broadcast Enter Activity State 1.
k_ra8_i3c_ccc_b_entas2	Broadcast Enter Activity State 2.
k_ra8_i3c_ccc_b_entas3	Broadcast Enter Activity State 3.
k_ra8_i3c_ccc_b_rstdaa	Broadcast Reset Dynamic Address Assignment.
k_ra8_i3c_ccc_b_entdaa	Broadcast Enter Dynamic Address Assignment.
k_ra8_i3c_ccc_b_rstact	Broadcast Peripheral Reset Action.
k_ra8_i3c_ccc_d_enec	Direct Enable Peripheral Events.
k_ra8_i3c_ccc_d_disec	Direct Disable Peripheral Events.
k_ra8_i3c_ccc_d_entas0	Direct Enter Activity State 0.
k_ra8_i3c_ccc_d_entas1	Direct Enter Activity State 1.
k_ra8_i3c_ccc_d_entas2	Direct Enter Activity State 2.
k_ra8_i3c_ccc_d_entas3	Direct Enter Activity State 3.
k_ra8_i3c_ccc_d_setdasa	Direct Set Dynamic Address from Static Address.
k_ra8_i3c_ccc_d_getmwl	Direct Get Max Write Length.
k_ra8_i3c_ccc_d_getmrl	Direct Get Max Read Length.
k_ra8_i3c_ccc_d_getpid	Direct Get Provisional ID.
k_ra8_i3c_ccc_d_getbcr	Direct Get Bus Characteristic Register.
k_ra8_i3c_ccc_d_getdcr	Direct Get Device Characteristic Register.
k_ra8_i3c_ccc_d_getstatus	Direct Get Device Status.
k_ra8_i3c_ccc_d_getxtime	Direct Get Exchange Timing Information.
k_ra8_i3c_ccc_d_rstact	Direct Peripheral Reset Action.
k_ra8_i3c_ccc_direct_mask	Bit set in direct CCC opcodes.

Definition at line 298 of file ra8_i3c_regs.h.

◆ ra8_i3c_cmd_desc_bits_t

enum ra8_i3c_cmd_desc_bits_t : uint32_t

NCMDQP command-descriptor field positions (FSP I3C_CMD_DESC_*).

The command queue accepts two 32-bit words per descriptor; this enum names every shift/mask used to assemble the first word, and the second-word XFER_LENGTH field for non-immediate transfers. See HUM Ch 40 "Command Descriptor" pp 2445-2701.

Enumerator
k_ra8_i3c_cmd_attr_shift	RA8 I3C cmd attr shift.
k_ra8_i3c_cmd_attr_xfer	Regular transfer attribute.
k_ra8_i3c_cmd_attr_immed	Immediate-data transfer attribute.
k_ra8_i3c_cmd_attr_addr_assgn	Address-assignment attribute.
k_ra8_i3c_cmd_tid_shift	Transaction ID position.
k_ra8_i3c_cmd_code_shift	CCC opcode position.
k_ra8_i3c_cmd_dev_index_shift	Device-table index.
k_ra8_i3c_cmd_cp_shift	Command Present (CCC) flag.
k_ra8_i3c_cmd_xfer_mode_shift	RA8 I3C cmd xfer mode shift.
k_ra8_i3c_cmd_addr_count_shift	ENTDAA device count.
k_ra8_i3c_cmd_rnw_shift	Read-not-Write direction bit.
k_ra8_i3c_cmd_roc_shift	Response-on-Completion.
k_ra8_i3c_cmd_toc_shift	Terminate-on-Completion (STOP).
k_ra8_i3c_cmd_immed_bytes_shift	Immediate byte count [24:23].
k_ra8_i3c_cmd_xfer_length_shift	Transfer length [31:16].
k_ra8_i3c_cmd_xfer_length_max	RA8 I3C cmd xfer length maximum.

Definition at line 336 of file ra8_i3c_regs.h.

◆ ra8_i3c_cmd_hdr_mode_t

enum ra8_i3c_cmd_hdr_mode_t : uint32_t

NCMDQP "transfer mode" attribute values for HDR transactions.

The HDR-mode field lives at NCMDQP word-0 bits [27:26]. See HUM Ch 40 "Command Descriptor" pp 2445-2701.

Enumerator
k_ra8_i3c_cmd_hdr_mode_sdr	Plain SDR transfer (default).
k_ra8_i3c_cmd_hdr_mode_ddr	HDR-DDR.
k_ra8_i3c_cmd_hdr_mode_ts	HDR-TS.
k_ra8_i3c_cmd_hdr_mode_mask	RA8 I3C cmd hdr mode mask.

Definition at line 237 of file ra8_i3c_regs.h.

◆ ra8_i3c_ibi_status_bits_t

enum ra8_i3c_ibi_status_bits_t : uint32_t

IBI status descriptor field positions (FSP I3C_IBI_STATUS_DESC_*).

The first word read from NIBIQP is an IBI status descriptor carrying length, IBI ID, error flags, and the IBI/HJ/MR type encoded by IBI_ST. See HUM Ch 40 "IBI Status Descriptor".

Enumerator
k_ra8_i3c_ibi_status_length_shift	RA8 I3C ibi status length shift.
k_ra8_i3c_ibi_status_length_mask	RA8 I3C ibi status length mask.
k_ra8_i3c_ibi_status_id_shift	RA8 I3C ibi status ID shift.
k_ra8_i3c_ibi_status_id_mask	RA8 I3C ibi status ID mask.
k_ra8_i3c_ibi_status_last_shift	RA8 I3C ibi status last shift.
k_ra8_i3c_ibi_status_ibi_st_mask	IBI status type bit 31.

Definition at line 377 of file ra8_i3c_regs.h.

◆ ra8_i3c_inst_bits_t

enum ra8_i3c_inst_bits_t : uint32_t

INST/INSTE/INIE bit positions.

Enumerator
k_ra8_i3c_inst_inef_mask	Internal Error Flag bit 10.

Definition at line 283 of file ra8_i3c_regs.h.

◆ ra8_i3c_limits_t

enum ra8_i3c_limits_t : uint8_t

Reserved-padding word counts for r_i3c_regs_t.

Each padding slot mirrors the FSP R_I3C0_Type RESERVED arrays, named by the register that immediately precedes the gap so that mismatches show up as a typed symbol in compiler errors.

Enumerator
k_ra8_i3c_instance_count	RA8 I3C instance count.
k_ra8_i3c_pad_after_prts	RESERVED[3] after PRTS.
k_ra8_i3c_pad_after_msdvad	RESERVED1 after MSDVAD.
k_ra8_i3c_pad_after_prsst	RESERVED2[2] after PRSST.
k_ra8_i3c_pad_after_instfc	RESERVED3 after INSTFC.
k_ra8_i3c_pad_after_dvct	RESERVED4[4] after DVCT.
k_ra8_i3c_pad_after_ibinctl	RESERVED5 after IBINCTL.
k_ra8_i3c_pad_after_svctl	RESERVED6[2] after SVCTL.
k_ra8_i3c_pad_after_tmoctl	RESERVED7 after TMOCTL.
k_ra8_i3c_pad_after_wuctl	RESERVED8 after WUCTL.
k_ra8_i3c_pad_after_scstr	RESERVED9[2] after SCSTRCTL.
k_ra8_i3c_pad_after_scstlctl	Reserved words 0x0BC..0x14F before NCMDQP.
k_ra8_i3c_pad_after_ntdtbp0	RESERVED14[8] after NTDTBP0.
k_ra8_i3c_pad_after_nrsqp	Reserved words 0x184..0x1DF before NTST.

Definition at line 68 of file ra8_i3c_regs.h.

◆ ra8_i3c_misc_t

enum ra8_i3c_misc_t : uint32_t

Miscellaneous protocol limits.

Enumerator
k_ra8_i3c_max_targets	Cap on ENTDAA device-table size.
k_ra8_i3c_pid_bytes	48-bit Provisional ID.
k_ra8_i3c_setdasa_payload_bytes	SETDASA carries one address byte.
k_ra8_i3c_immediate_max_bytes	Immediate-data transfer cap.
k_ra8_i3c_addr_mask	7-bit dynamic address mask.

Definition at line 390 of file ra8_i3c_regs.h.

◆ ra8_i3c_msdvad_bits_t

enum ra8_i3c_msdvad_bits_t : uint32_t

MSDVAD register bit positions / masks.

Enumerator
k_ra8_i3c_msdvad_mdyad_shift	MDYAD bits [22:16].
k_ra8_i3c_msdvad_mdyad_mask	RA8 I3C msdvad mdyad mask.
k_ra8_i3c_msdvad_mdyadv_mask	MDYADV bit 31.
k_ra8_i3c_msdvad_addr_max	7-bit dynamic address.

Definition at line 248 of file ra8_i3c_regs.h.

◆ ra8_i3c_nsdvad_bits_t

enum ra8_i3c_nsdvad_bits_t : uint32_t

NSDVAD (Peripheral Device Address Register) bit positions / masks.

Peripheral-mode counterpart of MSDVAD: SDYAD occupies bits [22:16], SDYADV (bit 31) marks the address as valid. See HUM Ch 40 "Peripheral Device Address Register" pp 2445-2701.

Enumerator
k_ra8_i3c_nsdvad_sdyad_shift	SDYAD bits [22:16].
k_ra8_i3c_nsdvad_sdyad_mask	RA8 I3C nsdvad sdyad mask.
k_ra8_i3c_nsdvad_sdyadv_mask	SDYADV bit 31.

Definition at line 209 of file ra8_i3c_regs.h.

◆ ra8_i3c_ntibivctl_bits_t

enum ra8_i3c_ntibivctl_bits_t : uint32_t

NTIBIVCTL (IBI Valid Control) field positions.

NTIBIVCTL.VLCNT[7:0] is the valid-entry count programmed by ra8_i3c_ibi_enable. HUM Ch 40 "IBI Valid Control" pp 2445-2701.

Enumerator
k_ra8_i3c_ntibivctl_vlcnt_mask	Valid-entry count [7:0].
k_ra8_i3c_ntibivctl_vlcnt_shift	RA8 I3C ntibivctl vlcnt shift.

Definition at line 224 of file ra8_i3c_regs.h.

◆ ra8_i3c_ntst_bits_t

enum ra8_i3c_ntst_bits_t : uint32_t

NTST (Normal Transfer Status) flag positions.

Enumerator
k_ra8_i3c_ntst_tdbef0_mask	Tx Buffer Empty bit 0.
k_ra8_i3c_ntst_rdbff0_mask	Rx Buffer Full bit 1.
k_ra8_i3c_ntst_ibiqeff_mask	IBI Queue Empty/Full bit 2.
k_ra8_i3c_ntst_cmdqef_mask	Cmd Queue Empty bit 3.
k_ra8_i3c_ntst_rspqff_mask	Rsp Queue Full bit 4.
k_ra8_i3c_ntst_rsqff_mask	Rx Status Queue Full bit 20.

Definition at line 359 of file ra8_i3c_regs.h.

◆ ra8_i3c_offset_t

enum ra8_i3c_offset_t : uint16_t

FSP-canonical byte offsets used by the layout asserts below.

Enumerator
k_ra8_i3c_off_bctl	RA8 I3C off bctl.
k_ra8_i3c_off_msdvad	RA8 I3C off msdvad.
k_ra8_i3c_off_rstctl	RA8 I3C off rstctl.
k_ra8_i3c_off_inst	RA8 I3C off inst.
k_ra8_i3c_off_dvct	RA8 I3C off dvct.
k_ra8_i3c_off_ibinctl	RA8 I3C off ibinctl.
k_ra8_i3c_off_bfctl	RA8 I3C off bfctl.
k_ra8_i3c_off_refckctl	RA8 I3C off refckctl.
k_ra8_i3c_off_ackctl	RA8 I3C off ackctl.
k_ra8_i3c_off_scstlctl	RA8 I3C off scstlctl.
k_ra8_i3c_off_ncmdqp	RA8 I3C off ncmdqp.
k_ra8_i3c_off_nrspqp	RA8 I3C off nrspqp.
k_ra8_i3c_off_ntdtbp0	RA8 I3C off ntdtbp0.
k_ra8_i3c_off_nibiqp	RA8 I3C off nibiqp.
k_ra8_i3c_off_nrsqp	RA8 I3C off nrsqp.
k_ra8_i3c_off_ntst	RA8 I3C off ntst.

Definition at line 416 of file ra8_i3c_regs.h.

◆ ra8_i3c_rstctl_bits_t

enum ra8_i3c_rstctl_bits_t : uint32_t

RSTCTL register bit positions / masks.

Bring-up sequence per HUM Ch 40 RSTCTL description: assert RI3CRST, wait for hardware to clear it, then optionally assert INTLRST + per-FIFO resets, then clear RSTCTL to release.

Enumerator
k_ra8_i3c_rstctl_ri3crst_mask	I3C software reset.
k_ra8_i3c_rstctl_cmdqrst_mask	Command queue reset.
k_ra8_i3c_rstctl_rspqrst_mask	Response queue reset.
k_ra8_i3c_rstctl_tdbrst_mask	Tx data buffer reset.
k_ra8_i3c_rstctl_rdbrst_mask	Rx data buffer reset.
k_ra8_i3c_rstctl_ibiqrst_mask	IBI queue reset.
k_ra8_i3c_rstctl_rsqrst_mask	Receive status queue reset.
k_ra8_i3c_rstctl_intlrst_mask	Internal software reset.
k_ra8_i3c_rstctl_fifo_mask	RA8 I3C rstctl FIFO mask.

Definition at line 264 of file ra8_i3c_regs.h.

Function Documentation

◆ ra8_i3c()

volatile r_i3c_regs_t * ra8_i3c ( void )

inlinestatic

Get pointer to I3C0.

Returns: Volatile pointer to instance 0 register window.

Definition at line 463 of file ra8_i3c_regs.h.

References k_ra8_i3c0_base_addr.

Referenced by ra8_i3c_bus_enable(), ra8_i3c_clear_status(), ra8_i3c_deinit(), ra8_i3c_dispatch(), ra8_i3c_dynamic_address_assign(), ra8_i3c_enter_stop(), ra8_i3c_get_status(), ra8_i3c_ibi_enable(), ra8_i3c_ibi_read(), ra8_i3c_init(), ra8_i3c_read(), ra8_i3c_recv_ccc(), ra8_i3c_reset_dynamic_addresses(), ra8_i3c_send_ccc(), ra8_i3c_set_address(), ra8_i3c_set_dynamic_address(), ra8_i3c_set_hdr_mode(), ra8_i3c_target_open(), and ra8_i3c_write().

Data Structures

Enumerations

Functions