ra8_i3c_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_i3c0_base_addr = 0x4035F000UL,         
  k_ra8_i3c1_base_addr = 0x4035F100UL,         
  k_ra8_i3c_base_addr  = k_ra8_i3c0_base_addr, 
} ra8_i3c_addr_t;

typedef enum : uint8_t {
  k_ra8_i3c_instance_count    = 2U, 
  k_ra8_i3c_pad_after_prts    = 3U, 
  k_ra8_i3c_pad_after_msdvad  = 1U, 
  k_ra8_i3c_pad_after_prsst   = 2U, 
  k_ra8_i3c_pad_after_instfc  = 1U, 
  k_ra8_i3c_pad_after_dvct    = 4U, 
  k_ra8_i3c_pad_after_ibinctl = 1U, 
  k_ra8_i3c_pad_after_svctl   = 2U, 
  k_ra8_i3c_pad_after_tmoctl  = 1U, 
  k_ra8_i3c_pad_after_wuctl   = 1U, 
  k_ra8_i3c_pad_after_scstr   = 2U, 
  /* From SCSTLCTL+1 (0x0B4) through CNDCTL+RESERVED13 ending at 0x14F is
   * 0x9C bytes = 39 words.  Covers SVTDLG0, STCTL, ATCTL, ATTRG, ATCCNTE,
   * CNDCTL and the surrounding RESERVED10..RESERVED13 padding.  None of
   * these registers are touched by the current driver -- the higher-
   * level peripheral-mode + sync-timing card-stack consumer can carve them
   * out of the gap when it lands. */
  k_ra8_i3c_pad_after_scstlctl = 37U, 
  /* The 0x158..0x17B gap is 8 reserved words (RESERVED14[8]) before NIBIQP. */
  k_ra8_i3c_pad_after_ntdtbp0 = 8U, 
  /* IBI-status-queue port immediately follows NIBIQP -> NRSQP at 0x180. */
  /* From NRSQP+1 (0x184) up to NTST at 0x1E0 is 0x5C bytes = 23 words.
   * Covers HCMDQP, HRSPQP, HTDTBP, NQTHCTL, NTBTHCTL0, NRQTHCTL,
   * HQTHCTL, HTBTHCTL, BST, BSTE, BIE, BSTFC and intervening
   * reserved padding -- none touched by the current driver. */
  k_ra8_i3c_pad_after_nrsqp = 23U, 
} ra8_i3c_limits_t;

typedef struct {
  volatile uint32_t PRTS;
  volatile uint32_t _r_prts[k_ra8_i3c_pad_after_prts];
  volatile uint32_t CECTL;  
  volatile uint32_t BCTL;   
  volatile uint32_t MSDVAD; 
  volatile uint32_t _r_msdvad[k_ra8_i3c_pad_after_msdvad];
  volatile uint32_t RSTCTL;
  volatile uint32_t PRSST;
  volatile uint32_t _r_prsst[k_ra8_i3c_pad_after_prsst];
  volatile uint32_t INST;   
  volatile uint32_t INSTE;  
  volatile uint32_t INIE;   
  volatile uint32_t INSTFC; 
  volatile uint32_t _r_instfc[k_ra8_i3c_pad_after_instfc];
  volatile uint32_t DVCT; 
  volatile uint32_t _r_dvct[k_ra8_i3c_pad_after_dvct];
  volatile uint32_t IBINCTL;
  volatile uint32_t _r_ibinctl[k_ra8_i3c_pad_after_ibinctl];
  volatile uint32_t BFCTL; 
  volatile uint32_t SVCTL; 
  volatile uint32_t _r_svctl[k_ra8_i3c_pad_after_svctl];
  volatile uint32_t REFCKCTL; 
  volatile uint32_t STDBR;    
  volatile uint32_t EXTBR;    
  volatile uint32_t BFRECDT;  
  volatile uint32_t BAVLCDT;  
  volatile uint32_t BIDLCDT;  
  volatile uint32_t OUTCTL;   
  volatile uint32_t INCTL;    
  volatile uint32_t TMOCTL;   
  volatile uint32_t _r_tmoctl[k_ra8_i3c_pad_after_tmoctl];
  volatile uint32_t WUCTL; 
  volatile uint32_t _r_wuctl[k_ra8_i3c_pad_after_wuctl];
  volatile uint32_t ACKCTL;   
  volatile uint32_t SCSTRCTL; 
  volatile uint32_t _r_scstr[k_ra8_i3c_pad_after_scstr];
  volatile uint32_t SCSTLCTL;  
  volatile uint32_t NSDVAD;    
  volatile uint32_t NTIBIVCTL; 
  volatile uint32_t _r_scstlctl[k_ra8_i3c_pad_after_scstlctl];
  volatile uint32_t NCMDQP;  
  volatile uint32_t NRSPQP;  
  volatile uint32_t NTDTBP0; 
  volatile uint32_t _r_ntdtbp0[k_ra8_i3c_pad_after_ntdtbp0];
  volatile uint32_t NIBIQP; 
  volatile uint32_t NRSQP;  
  volatile uint32_t _r_nrsqp[k_ra8_i3c_pad_after_nrsqp];
  volatile uint32_t NTST; 
} r_i3c_regs_t;

typedef enum : uint32_t {
  k_ra8_i3c_bctl_incba_mask    = 0x00000001UL, 
  k_ra8_i3c_bctl_bmds_mask     = 0x00000080UL, 
  k_ra8_i3c_bctl_hjackctl_mask = 0x00000100UL, 
  k_ra8_i3c_bctl_slve_mask     = 0x00010000UL, 
  k_ra8_i3c_bctl_abt_mask      = 0x20000000UL, 
  k_ra8_i3c_bctl_rsm_mask      = 0x40000000UL, 
  k_ra8_i3c_bctl_buse_mask     = 0x80000000UL, 
} ra8_i3c_bctl_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_nsdvad_sdyad_shift = 16U,          
  k_ra8_i3c_nsdvad_sdyad_mask  = 0x007F0000UL, 
  k_ra8_i3c_nsdvad_sdyadv_mask = 0x80000000UL, 
} ra8_i3c_nsdvad_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_ntibivctl_vlcnt_mask  = 0x000000FFUL, 
  k_ra8_i3c_ntibivctl_vlcnt_shift = 0U,           
} ra8_i3c_ntibivctl_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_cmd_hdr_mode_sdr  = 0UL,   
  k_ra8_i3c_cmd_hdr_mode_ddr  = 1UL,   
  k_ra8_i3c_cmd_hdr_mode_ts   = 2UL,   
  k_ra8_i3c_cmd_hdr_mode_mask = 0x3UL, 
} ra8_i3c_cmd_hdr_mode_t;

typedef enum : uint32_t {
  k_ra8_i3c_msdvad_mdyad_shift = 16U,          
  k_ra8_i3c_msdvad_mdyad_mask  = 0x007F0000UL, 
  k_ra8_i3c_msdvad_mdyadv_mask = 0x80000000UL, 
  k_ra8_i3c_msdvad_addr_max    = 0x7FUL,       
} ra8_i3c_msdvad_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_rstctl_ri3crst_mask = 0x00000001UL, 
  k_ra8_i3c_rstctl_cmdqrst_mask = 0x00000002UL, 
  k_ra8_i3c_rstctl_rspqrst_mask = 0x00000004UL, 
  k_ra8_i3c_rstctl_tdbrst_mask  = 0x00000008UL, 
  k_ra8_i3c_rstctl_rdbrst_mask  = 0x00000010UL, 
  k_ra8_i3c_rstctl_ibiqrst_mask = 0x00000020UL, 
  k_ra8_i3c_rstctl_rsqrst_mask  = 0x00000040UL, 
  k_ra8_i3c_rstctl_intlrst_mask = 0x00010000UL, 
  k_ra8_i3c_rstctl_fifo_mask =
    (k_ra8_i3c_rstctl_cmdqrst_mask | k_ra8_i3c_rstctl_rspqrst_mask | k_ra8_i3c_rstctl_tdbrst_mask |
     k_ra8_i3c_rstctl_rdbrst_mask | k_ra8_i3c_rstctl_ibiqrst_mask |
     k_ra8_i3c_rstctl_rsqrst_mask), 
} ra8_i3c_rstctl_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_inst_inef_mask = 0x00000400UL, 
} ra8_i3c_inst_bits_t;

typedef enum : uint8_t {
  k_ra8_i3c_ccc_b_enec      = 0x00U, 
  k_ra8_i3c_ccc_b_disec     = 0x01U, 
  k_ra8_i3c_ccc_b_entas0    = 0x02U, 
  k_ra8_i3c_ccc_b_entas1    = 0x03U, 
  k_ra8_i3c_ccc_b_entas2    = 0x04U, 
  k_ra8_i3c_ccc_b_entas3    = 0x05U, 
  k_ra8_i3c_ccc_b_rstdaa    = 0x06U, 
  k_ra8_i3c_ccc_b_entdaa    = 0x07U, 
  k_ra8_i3c_ccc_b_rstact    = 0x2AU, 
  k_ra8_i3c_ccc_d_enec      = 0x80U, 
  k_ra8_i3c_ccc_d_disec     = 0x81U, 
  k_ra8_i3c_ccc_d_entas0    = 0x82U, 
  k_ra8_i3c_ccc_d_entas1    = 0x83U, 
  k_ra8_i3c_ccc_d_entas2    = 0x84U, 
  k_ra8_i3c_ccc_d_entas3    = 0x85U, 
  k_ra8_i3c_ccc_d_setdasa   = 0x87U, 
  k_ra8_i3c_ccc_d_getmwl    = 0x8BU, 
  k_ra8_i3c_ccc_d_getmrl    = 0x8CU, 
  k_ra8_i3c_ccc_d_getpid    = 0x8DU, 
  k_ra8_i3c_ccc_d_getbcr    = 0x8EU, 
  k_ra8_i3c_ccc_d_getdcr    = 0x8FU, 
  k_ra8_i3c_ccc_d_getstatus = 0x90U, 
  k_ra8_i3c_ccc_d_getxtime  = 0x99U, 
  k_ra8_i3c_ccc_d_rstact    = 0x9AU, 
  k_ra8_i3c_ccc_direct_mask = 0x80U, 
} ra8_i3c_ccc_opcode_t;

typedef enum : uint32_t {
  k_ra8_i3c_cmd_attr_shift        = 0U,       
  k_ra8_i3c_cmd_attr_xfer         = 0U,       
  k_ra8_i3c_cmd_attr_immed        = 1U,       
  k_ra8_i3c_cmd_attr_addr_assgn   = 2U,       
  k_ra8_i3c_cmd_tid_shift         = 3U,       
  k_ra8_i3c_cmd_code_shift        = 7U,       
  k_ra8_i3c_cmd_dev_index_shift   = 16U,      
  k_ra8_i3c_cmd_cp_shift          = 15U,      
  k_ra8_i3c_cmd_xfer_mode_shift   = 26U,      
  k_ra8_i3c_cmd_addr_count_shift  = 26U,      
  k_ra8_i3c_cmd_rnw_shift         = 29U,      
  k_ra8_i3c_cmd_roc_shift         = 30U,      
  k_ra8_i3c_cmd_toc_shift         = 31U,      
  k_ra8_i3c_cmd_immed_bytes_shift = 23U,      
  k_ra8_i3c_cmd_xfer_length_shift = 16U,      
  k_ra8_i3c_cmd_xfer_length_max   = 0xFFFFUL, 
} ra8_i3c_cmd_desc_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_ntst_tdbef0_mask  = 0x00000001UL, 
  k_ra8_i3c_ntst_rdbff0_mask  = 0x00000002UL, 
  k_ra8_i3c_ntst_ibiqeff_mask = 0x00000004UL, 
  k_ra8_i3c_ntst_cmdqef_mask  = 0x00000008UL, 
  k_ra8_i3c_ntst_rspqff_mask  = 0x00000010UL, 
  k_ra8_i3c_ntst_rsqff_mask   = 0x00100000UL, 
} ra8_i3c_ntst_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_ibi_status_length_shift = 0U,           
  k_ra8_i3c_ibi_status_length_mask  = 0x000000FFUL, 
  k_ra8_i3c_ibi_status_id_shift     = 8U,           
  k_ra8_i3c_ibi_status_id_mask      = 0x0000FF00UL, 
  k_ra8_i3c_ibi_status_last_shift   = 24U,          
  k_ra8_i3c_ibi_status_ibi_st_mask  = 0x80000000UL, 
} ra8_i3c_ibi_status_bits_t;

typedef enum : uint32_t {
  k_ra8_i3c_max_targets           = 8U,    
  k_ra8_i3c_pid_bytes             = 6U,    
  k_ra8_i3c_setdasa_payload_bytes = 1U,    
  k_ra8_i3c_immediate_max_bytes   = 4U,    
  k_ra8_i3c_addr_mask             = 0x7FU, 
} ra8_i3c_misc_t;

typedef enum : uint32_t {
  k_ra8_i3c_byte_mask            = 0xFFU, 
  k_ra8_i3c_byte_shift           = 8U,    
  k_ra8_i3c_shift_b1             = 8U,    
  k_ra8_i3c_shift_b2             = 16U,   
  k_ra8_i3c_shift_b3             = 24U,   
  k_ra8_i3c_addr_shift_in_ibi_id = 1U,    
  k_ra8_i3c_word_size            = 4U,    
} ra8_i3c_byte_t;

typedef enum : uint16_t {
  k_ra8_i3c_off_bctl     = 0x014U, 
  k_ra8_i3c_off_msdvad   = 0x018U, 
  k_ra8_i3c_off_rstctl   = 0x020U, 
  k_ra8_i3c_off_inst     = 0x030U, 
  k_ra8_i3c_off_dvct     = 0x044U, 
  k_ra8_i3c_off_ibinctl  = 0x058U, 
  k_ra8_i3c_off_bfctl    = 0x060U, 
  k_ra8_i3c_off_refckctl = 0x070U, 
  k_ra8_i3c_off_ackctl   = 0x0A0U, 
  k_ra8_i3c_off_scstlctl = 0x0B0U, 
  k_ra8_i3c_off_ncmdqp   = 0x150U, 
  k_ra8_i3c_off_nrspqp   = 0x154U, 
  k_ra8_i3c_off_ntdtbp0  = 0x158U, 
  k_ra8_i3c_off_nibiqp   = 0x17CU, 
  k_ra8_i3c_off_nrsqp    = 0x180U, 
  k_ra8_i3c_off_ntst     = 0x1E0U, 
} ra8_i3c_offset_t;
 
/* Compile-time guards: every register that the I3C driver reads or
 * writes must sit at the FSP-canonical offset.  The constants on the
 * RHS come from the RA8D2 CMSIS device header
 * ``R7KA8D2KF_core0.h::R_I3C0_Type``. */
static_assert(offsetof(r_i3c_regs_t, INST) == (size_t)k_ra8_i3c_off_inst, "INST offset");
static_assert(offsetof(r_i3c_regs_t, MSDVAD) == (size_t)k_ra8_i3c_off_msdvad, "MSDVAD offset");
static_assert(offsetof(r_i3c_regs_t, BCTL) == (size_t)k_ra8_i3c_off_bctl, "BCTL offset");
static_assert(offsetof(r_i3c_regs_t, RSTCTL) == (size_t)k_ra8_i3c_off_rstctl, "RSTCTL offset");
static_assert(offsetof(r_i3c_regs_t, DVCT) == (size_t)k_ra8_i3c_off_dvct, "DVCT offset");
static_assert(offsetof(r_i3c_regs_t, IBINCTL) == (size_t)k_ra8_i3c_off_ibinctl, "IBINCTL offset");
static_assert(offsetof(r_i3c_regs_t, BFCTL) == (size_t)k_ra8_i3c_off_bfctl, "BFCTL offset");
static_assert(offsetof(r_i3c_regs_t, REFCKCTL) == (size_t)k_ra8_i3c_off_refckctl,
              "REFCKCTL offset");
static_assert(offsetof(r_i3c_regs_t, ACKCTL) == (size_t)k_ra8_i3c_off_ackctl, "ACKCTL offset");
static_assert(offsetof(r_i3c_regs_t, SCSTLCTL) == (size_t)k_ra8_i3c_off_scstlctl,
              "SCSTLCTL offset");
static_assert(offsetof(r_i3c_regs_t, NCMDQP) == (size_t)k_ra8_i3c_off_ncmdqp, "NCMDQP offset");
static_assert(offsetof(r_i3c_regs_t, NRSPQP) == (size_t)k_ra8_i3c_off_nrspqp, "NRSPQP offset");
static_assert(offsetof(r_i3c_regs_t, NTDTBP0) == (size_t)k_ra8_i3c_off_ntdtbp0, "NTDTBP0 offset");
static_assert(offsetof(r_i3c_regs_t, NIBIQP) == (size_t)k_ra8_i3c_off_nibiqp, "NIBIQP offset");
static_assert(offsetof(r_i3c_regs_t, NRSQP) == (size_t)k_ra8_i3c_off_nrsqp, "NRSQP offset");
static_assert(offsetof(r_i3c_regs_t, NTST) == (size_t)k_ra8_i3c_off_ntst, "NTST offset");

RA8_HW_REGISTER_ACCESS
static inline volatile r_i3c_regs_t* ra8_i3c(void)
{
  return (volatile r_i3c_regs_t*)k_ra8_i3c0_base_addr;
}
 
#ifdef __cplusplus
}
#endif