ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_i3c_regs_t Struct Reference

Partial RA8D2 I3C0 register window. More...

#include <ra8_i3c_regs.h>

Data Fields

volatile uint32_t PRTS
 +0x000 Protocol Selection Register.
volatile uint32_t _r_prts [k_ra8_i3c_pad_after_prts]
 Reserved.
volatile uint32_t CECTL
 +0x010 Clock Enable Control Register.
volatile uint32_t BCTL
 +0x014 Bus Control Register.
volatile uint32_t MSDVAD
 +0x018 Controller Device Address Register.
volatile uint32_t _r_msdvad [k_ra8_i3c_pad_after_msdvad]
 Reserved.
volatile uint32_t RSTCTL
 +0x020 Reset Control Register.
volatile uint32_t PRSST
 +0x024 Present State Register.
volatile uint32_t _r_prsst [k_ra8_i3c_pad_after_prsst]
 Reserved.
volatile uint32_t INST
 +0x030 Internal Status Register.
volatile uint32_t INSTE
 +0x034 Internal Status Enable Register.
volatile uint32_t INIE
 +0x038 Internal Interrupt Enable Register.
volatile uint32_t INSTFC
 +0x03C Internal Status Force Register.
volatile uint32_t _r_instfc [k_ra8_i3c_pad_after_instfc]
 Reserved.
volatile uint32_t DVCT
 +0x044 Device Characteristic Table Register.
volatile uint32_t _r_dvct [k_ra8_i3c_pad_after_dvct]
 Reserved.
volatile uint32_t IBINCTL
 +0x058 IBI Notify Control Register.
volatile uint32_t _r_ibinctl [k_ra8_i3c_pad_after_ibinctl]
 Reserved.
volatile uint32_t BFCTL
 +0x060 Bus Function Control Register.
volatile uint32_t SVCTL
 +0x064 Peripheral Control Register.
volatile uint32_t _r_svctl [k_ra8_i3c_pad_after_svctl]
 Reserved.
volatile uint32_t REFCKCTL
 +0x070 Reference Clock Control Register.
volatile uint32_t STDBR
 +0x074 Standard Bit Rate Register.
volatile uint32_t EXTBR
 +0x078 Extended Bit Rate Register.
volatile uint32_t BFRECDT
 +0x07C Bus Free Condition Detection Time Register.
volatile uint32_t BAVLCDT
 +0x080 Bus Available Condition Detection Time Register.
volatile uint32_t BIDLCDT
 +0x084 Bus Idle Condition Detection Time Register.
volatile uint32_t OUTCTL
 +0x088 Output Control Register.
volatile uint32_t INCTL
 +0x08C Input Control Register.
volatile uint32_t TMOCTL
 +0x090 Timeout Control Register.
volatile uint32_t _r_tmoctl [k_ra8_i3c_pad_after_tmoctl]
 Reserved.
volatile uint32_t WUCTL
 +0x098 Wake-Up Unit Control Register.
volatile uint32_t _r_wuctl [k_ra8_i3c_pad_after_wuctl]
 Reserved.
volatile uint32_t ACKCTL
 +0x0A0 Acknowledge Control Register.
volatile uint32_t SCSTRCTL
 +0x0A4 SCL Stretch Control Register.
volatile uint32_t _r_scstr [k_ra8_i3c_pad_after_scstr]
 Reserved.
volatile uint32_t SCSTLCTL
 +0x0B0 SCL Stalling Control Register.
volatile uint32_t NSDVAD
 +0x0B4 Peripheral Device Address Register (peripheral-mode dynamic address + valid).
volatile uint32_t NTIBIVCTL
 +0x0B8 IBI Valid Control Register (peripheral-side IBI queue valid count).
volatile uint32_t _r_scstlctl [k_ra8_i3c_pad_after_scstlctl]
 Reserved.
volatile uint32_t NCMDQP
 +0x150 Normal Command Queue Port Register.
volatile uint32_t NRSPQP
 +0x154 Normal Response Queue Port Register.
volatile uint32_t NTDTBP0
 +0x158 Normal Transfer Data Buffer Port Register 0.
volatile uint32_t _r_ntdtbp0 [k_ra8_i3c_pad_after_ntdtbp0]
 0x15C..0x17B reserved gap.
volatile uint32_t NIBIQP
 +0x17C Normal IBI Queue Port Register.
volatile uint32_t NRSQP
 +0x180 Normal Receive Status Queue Port Register.
volatile uint32_t _r_nrsqp [k_ra8_i3c_pad_after_nrsqp]
 0x184..0x1DF reserved gap.
volatile uint32_t NTST
 +0x1E0 Normal Transfer Status Register.

Detailed Description

Partial RA8D2 I3C0 register window.

Mirrors the FSP R_I3C0_Type layout up through NTST at offset 0x1E0. See HUM Ch 40 "I3C Bus Interface (I3C)" pp 2445-2701 for the field-level descriptions. Members beyond that offset (NTSTE, NTIE, HTST, BCST, SVST, DATBASn ...) are not declared because no driver code touches them yet.

cppcheck cannot see the unit-test consumers that read every field, so the unused-field warning is suppressed with a begin/end pair instead of per-member annotations.

Definition at line 112 of file ra8_i3c_regs.h.

Field Documentation

◆ _r_dvct

volatile uint32_t r_i3c_regs_t::_r_dvct[k_ra8_i3c_pad_after_dvct]

Reserved.

Definition at line 136 of file ra8_i3c_regs.h.

◆ _r_ibinctl

volatile uint32_t r_i3c_regs_t::_r_ibinctl[k_ra8_i3c_pad_after_ibinctl]

Reserved.

Definition at line 140 of file ra8_i3c_regs.h.

◆ _r_instfc

volatile uint32_t r_i3c_regs_t::_r_instfc[k_ra8_i3c_pad_after_instfc]

Reserved.

Definition at line 133 of file ra8_i3c_regs.h.

◆ _r_msdvad

volatile uint32_t r_i3c_regs_t::_r_msdvad[k_ra8_i3c_pad_after_msdvad]

Reserved.

Definition at line 121 of file ra8_i3c_regs.h.

◆ _r_nrsqp

volatile uint32_t r_i3c_regs_t::_r_nrsqp[k_ra8_i3c_pad_after_nrsqp]

0x184..0x1DF reserved gap.

Definition at line 182 of file ra8_i3c_regs.h.

◆ _r_ntdtbp0

volatile uint32_t r_i3c_regs_t::_r_ntdtbp0[k_ra8_i3c_pad_after_ntdtbp0]

0x15C..0x17B reserved gap.

Definition at line 178 of file ra8_i3c_regs.h.

◆ _r_prsst

volatile uint32_t r_i3c_regs_t::_r_prsst[k_ra8_i3c_pad_after_prsst]

Reserved.

Definition at line 127 of file ra8_i3c_regs.h.

◆ _r_prts

volatile uint32_t r_i3c_regs_t::_r_prts[k_ra8_i3c_pad_after_prts]

Reserved.

Definition at line 116 of file ra8_i3c_regs.h.

◆ _r_scstlctl

volatile uint32_t r_i3c_regs_t::_r_scstlctl[k_ra8_i3c_pad_after_scstlctl]

Reserved.

Definition at line 173 of file ra8_i3c_regs.h.

◆ _r_scstr

volatile uint32_t r_i3c_regs_t::_r_scstr[k_ra8_i3c_pad_after_scstr]

Reserved.

Definition at line 162 of file ra8_i3c_regs.h.

◆ _r_svctl

volatile uint32_t r_i3c_regs_t::_r_svctl[k_ra8_i3c_pad_after_svctl]

Reserved.

Definition at line 144 of file ra8_i3c_regs.h.

◆ _r_tmoctl

volatile uint32_t r_i3c_regs_t::_r_tmoctl[k_ra8_i3c_pad_after_tmoctl]

Reserved.

Definition at line 155 of file ra8_i3c_regs.h.

◆ _r_wuctl

volatile uint32_t r_i3c_regs_t::_r_wuctl[k_ra8_i3c_pad_after_wuctl]

Reserved.

Definition at line 158 of file ra8_i3c_regs.h.

◆ ACKCTL

volatile uint32_t r_i3c_regs_t::ACKCTL

+0x0A0 Acknowledge Control Register.

Definition at line 159 of file ra8_i3c_regs.h.

◆ BAVLCDT

volatile uint32_t r_i3c_regs_t::BAVLCDT

+0x080 Bus Available Condition Detection Time Register.

Definition at line 149 of file ra8_i3c_regs.h.

◆ BCTL

volatile uint32_t r_i3c_regs_t::BCTL

+0x014 Bus Control Register.

Definition at line 118 of file ra8_i3c_regs.h.

Referenced by internal_ra8_i3c_reset_sequence(), ra8_i3c_bus_enable(), ra8_i3c_deinit(), ra8_i3c_enter_stop(), and ra8_i3c_target_open().

◆ BFCTL

volatile uint32_t r_i3c_regs_t::BFCTL

+0x060 Bus Function Control Register.

Definition at line 141 of file ra8_i3c_regs.h.

◆ BFRECDT

volatile uint32_t r_i3c_regs_t::BFRECDT

+0x07C Bus Free Condition Detection Time Register.

Definition at line 148 of file ra8_i3c_regs.h.

◆ BIDLCDT

volatile uint32_t r_i3c_regs_t::BIDLCDT

+0x084 Bus Idle Condition Detection Time Register.

Definition at line 150 of file ra8_i3c_regs.h.

◆ CECTL

volatile uint32_t r_i3c_regs_t::CECTL

+0x010 Clock Enable Control Register.

Definition at line 117 of file ra8_i3c_regs.h.

Referenced by internal_ra8_i3c_reset_sequence(), ra8_i3c_deinit(), and ra8_i3c_enter_stop().

◆ DVCT

volatile uint32_t r_i3c_regs_t::DVCT

+0x044 Device Characteristic Table Register.

Definition at line 134 of file ra8_i3c_regs.h.

◆ EXTBR

volatile uint32_t r_i3c_regs_t::EXTBR

+0x078 Extended Bit Rate Register.

Definition at line 147 of file ra8_i3c_regs.h.

◆ IBINCTL

volatile uint32_t r_i3c_regs_t::IBINCTL

+0x058 IBI Notify Control Register.

Definition at line 138 of file ra8_i3c_regs.h.

◆ INCTL

volatile uint32_t r_i3c_regs_t::INCTL

+0x08C Input Control Register.

Definition at line 152 of file ra8_i3c_regs.h.

◆ INIE

volatile uint32_t r_i3c_regs_t::INIE

+0x038 Internal Interrupt Enable Register.

Definition at line 130 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_deinit(), and ra8_i3c_init().

◆ INST

volatile uint32_t r_i3c_regs_t::INST

+0x030 Internal Status Register.

Definition at line 128 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_clear_status(), ra8_i3c_dispatch(), ra8_i3c_get_status(), and ra8_i3c_init().

◆ INSTE

volatile uint32_t r_i3c_regs_t::INSTE

+0x034 Internal Status Enable Register.

Definition at line 129 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_deinit(), and ra8_i3c_init().

◆ INSTFC

volatile uint32_t r_i3c_regs_t::INSTFC

+0x03C Internal Status Force Register.

Definition at line 131 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_init().

◆ MSDVAD

volatile uint32_t r_i3c_regs_t::MSDVAD

+0x018 Controller Device Address Register.

Definition at line 119 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_init(), and ra8_i3c_set_address().

◆ NCMDQP

volatile uint32_t r_i3c_regs_t::NCMDQP

+0x150 Normal Command Queue Port Register.

Definition at line 174 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_dynamic_address_assign(), ra8_i3c_read(), ra8_i3c_recv_ccc(), ra8_i3c_reset_dynamic_addresses(), ra8_i3c_send_ccc(), ra8_i3c_set_dynamic_address(), ra8_i3c_set_hdr_mode(), and ra8_i3c_write().

◆ NIBIQP

volatile uint32_t r_i3c_regs_t::NIBIQP

+0x17C Normal IBI Queue Port Register.

Definition at line 179 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_ibi_read().

◆ NRSPQP

volatile uint32_t r_i3c_regs_t::NRSPQP

+0x154 Normal Response Queue Port Register.

Definition at line 175 of file ra8_i3c_regs.h.

◆ NRSQP

volatile uint32_t r_i3c_regs_t::NRSQP

+0x180 Normal Receive Status Queue Port Register.

Definition at line 180 of file ra8_i3c_regs.h.

◆ NSDVAD

volatile uint32_t r_i3c_regs_t::NSDVAD

+0x0B4 Peripheral Device Address Register (peripheral-mode dynamic address + valid).

See HUM Ch 40 "Peripheral Device Address" pp 2445-2701.

Definition at line 164 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_target_open().

◆ NTDTBP0

volatile uint32_t r_i3c_regs_t::NTDTBP0

+0x158 Normal Transfer Data Buffer Port Register 0.

Definition at line 176 of file ra8_i3c_regs.h.

Referenced by internal_ra8_i3c_fifo_read(), and internal_ra8_i3c_fifo_write().

◆ NTIBIVCTL

volatile uint32_t r_i3c_regs_t::NTIBIVCTL

+0x0B8 IBI Valid Control Register (peripheral-side IBI queue valid count).

See HUM Ch 40 "IBI Valid Control" pp 2445-2701.

Definition at line 168 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_ibi_enable().

◆ NTST

volatile uint32_t r_i3c_regs_t::NTST

+0x1E0 Normal Transfer Status Register.

Definition at line 183 of file ra8_i3c_regs.h.

Referenced by ra8_i3c_dynamic_address_assign(), ra8_i3c_ibi_read(), ra8_i3c_read(), ra8_i3c_recv_ccc(), ra8_i3c_reset_dynamic_addresses(), ra8_i3c_send_ccc(), ra8_i3c_set_dynamic_address(), ra8_i3c_set_hdr_mode(), and ra8_i3c_write().

◆ OUTCTL

volatile uint32_t r_i3c_regs_t::OUTCTL

+0x088 Output Control Register.

Definition at line 151 of file ra8_i3c_regs.h.

◆ PRSST

volatile uint32_t r_i3c_regs_t::PRSST

+0x024 Present State Register.

Definition at line 125 of file ra8_i3c_regs.h.

◆ PRTS

volatile uint32_t r_i3c_regs_t::PRTS

+0x000 Protocol Selection Register.

Definition at line 114 of file ra8_i3c_regs.h.

Referenced by internal_ra8_i3c_reset_sequence().

◆ REFCKCTL

volatile uint32_t r_i3c_regs_t::REFCKCTL

+0x070 Reference Clock Control Register.

Definition at line 145 of file ra8_i3c_regs.h.

◆ RSTCTL

volatile uint32_t r_i3c_regs_t::RSTCTL

+0x020 Reset Control Register.

Definition at line 123 of file ra8_i3c_regs.h.

Referenced by internal_ra8_i3c_reset_sequence().

◆ SCSTLCTL

volatile uint32_t r_i3c_regs_t::SCSTLCTL

+0x0B0 SCL Stalling Control Register.

Definition at line 163 of file ra8_i3c_regs.h.

◆ SCSTRCTL

volatile uint32_t r_i3c_regs_t::SCSTRCTL

+0x0A4 SCL Stretch Control Register.

Definition at line 160 of file ra8_i3c_regs.h.

◆ STDBR

volatile uint32_t r_i3c_regs_t::STDBR

+0x074 Standard Bit Rate Register.

Definition at line 146 of file ra8_i3c_regs.h.

◆ SVCTL

volatile uint32_t r_i3c_regs_t::SVCTL

+0x064 Peripheral Control Register.

Definition at line 142 of file ra8_i3c_regs.h.

◆ TMOCTL

volatile uint32_t r_i3c_regs_t::TMOCTL

+0x090 Timeout Control Register.

Definition at line 153 of file ra8_i3c_regs.h.

◆ WUCTL

volatile uint32_t r_i3c_regs_t::WUCTL

+0x098 Wake-Up Unit Control Register.

Definition at line 156 of file ra8_i3c_regs.h.

The documentation for this struct was generated from the following file: