ra8_i2c_peripheral.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_i2c.h"
#include "ra8_i2c_internal.h"
#include "ra8_i2c_regs.h"

typedef enum : uint32_t {
  k_ra8_i2c_peripheral_poll_limit = 200000U,
} ra8_i2c_peripheral_limits_t;

typedef enum : uint8_t {
  k_ra8_i2c_peripheral_addr_7b_max = 0x7FU, 
  k_ra8_i2c_peripheral_slot_max    = 2U,    
  k_ra8_i2c_peripheral_addr_shift = (uint8_t)k_ra8_i2c_sarl_sva_pos,
  k_ra8_i2c_peripheral_saru_7bit = 0U,
  k_ra8_i2c_peripheral_icier_arm =
    (uint8_t)((1U << (uint8_t)k_ra8_i2c_icier_rie_pos) | (1U << (uint8_t)k_ra8_i2c_icier_tie_pos) |
              (1U << (uint8_t)k_ra8_i2c_icier_spie_pos)),
} ra8_i2c_peripheral_const_t;
 
/* =============================================================================
 * Pure decision predicates (TU-external for MC/DC -- see ra8_i2c_internal.h).
 * =============================================================================
 */
 
bool priv_ra8_i2c_internal_peripheral_poll_done(uint8_t icsr1, uint8_t icsr2)
{
  return ((icsr1 & (uint8_t)k_ra8_i2c_msk_icsr1_match) != 0U) ||
         ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_stop) != 0U);
}
 
bool priv_ra8_i2c_internal_peripheral_rx_continue(uint8_t  icsr2,
                                                  uint32_t received,
                                                  uint32_t capacity)
{
  return ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_stop) == 0U) && (received < capacity);
}
 
bool priv_ra8_i2c_internal_peripheral_tx_done(uint8_t icsr2)
{
  return ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_nackf) != 0U) ||
         ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_tend) != 0U);
}
 
bool priv_ra8_i2c_internal_peripheral_tx_continue(uint8_t icsr2, uint32_t sent, uint32_t len)
{
  return ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_nackf) == 0U) && (sent < len);
}
 
/* =============================================================================
 * Local helpers.
 * =============================================================================
 */

RA8_INTERNAL static ra8_i2c_peripheral_event_t internal_i2c_target_classify(uint8_t icsr1,
                                                                            uint8_t iccr2)
{
  if ((icsr1 & (uint8_t)k_ra8_i2c_msk_icsr1_match) == 0U) {
    return k_ra8_i2c_peripheral_event_none;
  }
  if ((iccr2 & (uint8_t)k_ra8_i2c_msk_iccr2_trs) != 0U) {
    return k_ra8_i2c_peripheral_event_read;
  }
  return k_ra8_i2c_peripheral_event_write;
}

RA8_INTERNAL static ra8_err_t internal_i2c_target_wait(volatile const r_i2c_regs_t* reg,
                                                       uint8_t                      mask)
{
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_i2c_peripheral_poll_limit; i++) {
    /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
    if ((reg->ICSR2 & mask) != 0U) {
      return k_ra8_ok;
    }
  }
  return k_ra8_err_hw_timeout;
}

RA8_INTERNAL static void
internal_i2c_target_set_addr(volatile r_i2c_regs_t* reg, uint8_t slot, uint8_t addr_7b)
{
  const uint8_t sarl = (uint8_t)((uint32_t)addr_7b << (uint32_t)k_ra8_i2c_peripheral_addr_shift);
  switch (slot) {
    case (uint8_t)k_ra8_i2c_peripheral_slot_0:
      /* HUM Ch 39.2.13 "SARLy : own-address register Ly" p 2390 */
      reg->SARL0 = sarl;
      /* HUM Ch 39.2.14 "SARUy : own-address register Uy" p 2391 */
      reg->SARU0 = (uint8_t)k_ra8_i2c_peripheral_saru_7bit;
      break;
    case (uint8_t)k_ra8_i2c_peripheral_slot_1:
      /* HUM Ch 39.2.13 "SARLy : own-address register Ly" p 2390 */
      reg->SARL1 = sarl;
      /* HUM Ch 39.2.14 "SARUy : own-address register Uy" p 2391 */
      reg->SARU1 = (uint8_t)k_ra8_i2c_peripheral_saru_7bit;
      break;
    default:
      /* HUM Ch 39.2.13 "SARLy : own-address register Ly" p 2390 */
      reg->SARL2 = sarl;
      /* HUM Ch 39.2.14 "SARUy : own-address register Uy" p 2391 */
      reg->SARU2 = (uint8_t)k_ra8_i2c_peripheral_saru_7bit;
      break;
  }
}

RA8_INTERNAL static uint8_t internal_i2c_target_icser_mask(uint8_t slot, bool general_call)
{
  uint8_t mask = (uint8_t)((uint32_t)k_ra8_i2c_msk_icser_sar0e << (uint32_t)slot);
  if (general_call) {
    mask |= (uint8_t)k_ra8_i2c_msk_icser_gcae;
  }
  return mask;
}

ra8_err_t priv_ra8_i2c_internal_target_drain_rx(volatile r_i2c_regs_t* reg,
                                                uint8_t*               buf,
                                                uint32_t               capacity,
                                                uint32_t*              out_count)
{
  uint32_t  count = 0U;
  ra8_err_t err   = k_ra8_ok;
  for (uint32_t i = 0U; i <= capacity; i++) {
    err = internal_i2c_target_wait(
      reg,
      (uint8_t)((uint8_t)k_ra8_i2c_msk_icsr2_rdrf | (uint8_t)k_ra8_i2c_msk_icsr2_stop));
    if (err != k_ra8_ok) {
      break;
    }
    /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
    const uint8_t icsr2 = reg->ICSR2;
    if (!priv_ra8_i2c_internal_peripheral_rx_continue(icsr2, count, capacity)) {
      /* STOP detected or buffer full: drain a final pending byte if room. */
      if (((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_rdrf) != 0U) && (count < capacity)) {
        /* HUM Ch 39.2.18 "ICDRR : I2C Bus Receive Data Register" p 2393 */
        buf[count] = reg->ICDRR;
        count++;
      }
      break;
    }
    if ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_rdrf) != 0U) {
      /* HUM Ch 39.2.18 "ICDRR : I2C Bus Receive Data Register" p 2393 */
      buf[count] = reg->ICDRR;
      count++;
    }
  }
  *out_count = count;
  return err;
}

RA8_INTERNAL static void internal_i2c_target_fill_tx(volatile r_i2c_regs_t* reg,
                                                     const uint8_t*         data,
                                                     uint32_t               len,
                                                     uint32_t*              out_sent)
{
  uint32_t sent = 0U;
  for (uint32_t i = 0U; i <= len; i++) {
    /* Step 3 (peripheral transmit): wait for TDRE before each byte.
     * HUM Ch 39.3.5 "Peripheral Transmit Operation" p 2405 */
    if (internal_i2c_target_wait(reg, (uint8_t)k_ra8_i2c_msk_icsr2_tdre) != k_ra8_ok) {
      break;
    }
    /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
    const uint8_t icsr2 = reg->ICSR2;
    if (!priv_ra8_i2c_internal_peripheral_tx_continue(icsr2, sent, len)) {
      break;
    }
    /* HUM Ch 39.2.17 "ICDRT : I2C Bus Transmit Data Register" p 2393 */
    reg->ICDRT = data[sent];
    sent++;
  }
  *out_sent = sent;
}

RA8_INTERNAL static bool internal_i2c_target_finish_tx(volatile r_i2c_regs_t* reg)
{
  /* Step 4: wait for the controller's TEND or NACK to mark frame end. */
  (void)internal_i2c_target_wait(
    reg,
    (uint8_t)((uint8_t)k_ra8_i2c_msk_icsr2_tend | (uint8_t)k_ra8_i2c_msk_icsr2_nackf));
  /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
  const bool ended = priv_ra8_i2c_internal_peripheral_tx_done(reg->ICSR2);
 
  /* Step 5: dummy-read ICDRR to release SCL.
   * HUM Ch 39.2.18 "ICDRR : I2C Bus Receive Data Register" p 2393 */
  (void)reg->ICDRR;
 
  /* Step 7: clear NACKF and STOP (W0C) for the next transfer.
   * HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2 -- W0C" p 2384 */
  reg->ICSR2 = (uint8_t)(reg->ICSR2 & (uint8_t)~(uint8_t)((uint8_t)k_ra8_i2c_msk_icsr2_nackf |
                                                          (uint8_t)k_ra8_i2c_msk_icsr2_stop));
  return ended;
}
 
/* =============================================================================
 * Public target-role API.
 * =============================================================================
 */
 
ra8_err_t ra8_i2c_peripheral_init(uint8_t channel, const ra8_i2c_peripheral_cfg_t* cfg)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  RA8_CHECK_NULL_PTR(reg, g_i2c_tag, "i2c_target_init: channel");
  RA8_CHECK_NULL_PTR(cfg, g_i2c_tag, "i2c_target_init: cfg");
  if (cfg->own_addr_7b > (uint8_t)k_ra8_i2c_peripheral_addr_7b_max) {
    return k_ra8_err_invalid_arg;
  }
  if ((uint8_t)cfg->slot > (uint8_t)k_ra8_i2c_peripheral_slot_max) {
    return k_ra8_err_invalid_arg;
  }
 
  const uint8_t slot = (uint8_t)cfg->slot;
  internal_i2c_target_set_addr(reg, slot, cfg->own_addr_7b);
 
  /* HUM Ch 39.2.7 "ICSER : I2C Bus Status Enable Register" p 2380 */
  reg->ICSER = internal_i2c_target_icser_mask(slot, cfg->general_call);
 
  if (cfg->clock_stretch) {
    /* HUM Ch 39.2.5 "ICMR3 : I2C Bus Mode Register 3 -- WAIT" p 2376 */
    reg->ICMR3 = (uint8_t)(reg->ICMR3 | (uint8_t)k_ra8_i2c_msk_icmr3_wait);
  }
 
  if (cfg->irq_enable) {
    /* HUM Ch 39.2.8 "ICIER : I2C Bus Interrupt Enable Register" p 2381 */
    reg->ICIER = (uint8_t)(reg->ICIER | (uint8_t)k_ra8_i2c_peripheral_icier_arm);
  }
 
  s_i2c_state[channel].peripheral_active = true;
  return k_ra8_ok;
}
 
ra8_err_t ra8_i2c_peripheral_deinit(uint8_t channel)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (!s_i2c_state[channel].peripheral_active) {
    return k_ra8_err_not_initialized;
  }
  /* HUM Ch 39.2.7 "ICSER : I2C Bus Status Enable Register" p 2380 */
  reg->ICSER = 0U;
  /* HUM Ch 39.2.5 "ICMR3 : I2C Bus Mode Register 3 -- WAIT" p 2376 */
  reg->ICMR3 = (uint8_t)(reg->ICMR3 & (uint8_t)~(uint8_t)k_ra8_i2c_msk_icmr3_wait);
  /* HUM Ch 39.2.8 "ICIER : I2C Bus Interrupt Enable Register" p 2381 */
  reg->ICIER = (uint8_t)(reg->ICIER & (uint8_t)~(uint8_t)k_ra8_i2c_peripheral_icier_arm);
  s_i2c_state[channel].peripheral_active = false;
  return k_ra8_ok;
}
 
ra8_err_t ra8_i2c_peripheral_poll(uint8_t channel, ra8_i2c_peripheral_event_t* out_event)
{
  volatile const r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  RA8_CHECK_NULL_PTR(reg, g_i2c_tag, "i2c_target_poll: channel");
  RA8_CHECK_NULL_PTR(out_event, g_i2c_tag, "i2c_target_poll: out_event");
  *out_event = k_ra8_i2c_peripheral_event_none;
  if (!s_i2c_state[channel].peripheral_active) {
    return k_ra8_err_not_initialized;
  }
 
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_i2c_peripheral_poll_limit; i++) {
    /* HUM Ch 39.2.9 "ICSR1 : I2C Bus Status Register 1" p 2382 */
    const uint8_t icsr1 = reg->ICSR1;
    /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
    const uint8_t icsr2 = reg->ICSR2;
    if (priv_ra8_i2c_internal_peripheral_poll_done(icsr1, icsr2)) {
      break;
    }
  }
 
  /* HUM Ch 39.2.9 "ICSR1 : I2C Bus Status Register 1" p 2382 */
  const uint8_t icsr1 = reg->ICSR1;
  /* HUM Ch 39.2.2 "ICCR2 : I2C Bus Control Register 2 -- TRS" p 2371 */
  const uint8_t iccr2 = reg->ICCR2;
  *out_event          = internal_i2c_target_classify(icsr1, iccr2);
  return k_ra8_ok;
}
 
ra8_err_t
ra8_i2c_peripheral_receive(uint8_t channel, uint8_t* buf, uint32_t capacity, uint32_t* out_received)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  RA8_CHECK_NULL_PTR(reg, g_i2c_tag, "i2c_target_receive: channel");
  RA8_CHECK_NULL_PTR(buf, g_i2c_tag, "i2c_target_receive: buf");
  RA8_CHECK_NULL_PTR(out_received, g_i2c_tag, "i2c_target_receive: out_received");
  *out_received = 0U;
  if (capacity == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (!s_i2c_state[channel].peripheral_active) {
    return k_ra8_err_not_initialized;
  }
 
  /* Step 3 (peripheral receive): the address-phase RDRF, then dummy-read
   * ICDRR to discard the matched address byte and clear RDRF.
   * HUM Ch 39.3.6 "Peripheral Receive Operation" p 2408 */
  ra8_err_t err = internal_i2c_target_wait(reg, (uint8_t)k_ra8_i2c_msk_icsr2_rdrf);
  if (err != k_ra8_ok) {
    return err;
  }
  /* HUM Ch 39.2.18 "ICDRR : I2C Bus Receive Data Register" p 2393 */
  (void)reg->ICDRR;
 
  /* Steps 4-5: drain data bytes until STOP or the buffer fills. */
  uint32_t count = 0U;
  err            = priv_ra8_i2c_internal_target_drain_rx(reg, buf, capacity, &count);
 
  /* Step 6: clear the STOP flag (W0C) for the next transfer.
   * HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2 -- STOP W0C" p 2384 */
  reg->ICSR2    = (uint8_t)(reg->ICSR2 & (uint8_t)~(uint8_t)k_ra8_i2c_msk_icsr2_stop);
  *out_received = count;
  return (count == 0U) ? err : k_ra8_ok;
}
 
ra8_err_t
ra8_i2c_peripheral_transmit(uint8_t channel, const uint8_t* data, uint32_t len, uint32_t* out_sent)
{
  volatile r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  RA8_CHECK_NULL_PTR(reg, g_i2c_tag, "i2c_target_transmit: channel");
  RA8_CHECK_NULL_PTR(data, g_i2c_tag, "i2c_target_transmit: data");
  RA8_CHECK_NULL_PTR(out_sent, g_i2c_tag, "i2c_target_transmit: out_sent");
  *out_sent = 0U;
  if (len == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (!s_i2c_state[channel].peripheral_active) {
    return k_ra8_err_not_initialized;
  }
 
  /* Step 3: push data bytes to ICDRT until NACK or every byte is queued. */
  uint32_t sent = 0U;
  internal_i2c_target_fill_tx(reg, data, len, &sent);
 
  /* Steps 4-7: confirm the controller ended the read, release SCL, clear
   * NACKF / STOP. ``ended`` is k_ra8_ok-equivalent: the end-of-frame poll only
   * times out (ended == false) when no TEND / NACK ever arrives, which is the
   * single failure mode for both an empty and a non-empty transmit. */
  const bool ended = internal_i2c_target_finish_tx(reg);
  *out_sent        = sent;
  return ended ? k_ra8_ok : k_ra8_err_hw_timeout;
}
 
/* =============================================================================
 * Event dispatch -- attached-callback path (RIIC ISR or poll loop).
 * =============================================================================
 */

RA8_INTERNAL static ra8_i2c_peripheral_event_t
internal_i2c_dispatch_event(uint8_t icsr1, uint8_t icsr2, uint8_t iccr2)
{
  const ra8_i2c_peripheral_event_t match = internal_i2c_target_classify(icsr1, iccr2);
  if (match != k_ra8_i2c_peripheral_event_none) {
    return match;
  }
  if ((icsr2 & (uint8_t)k_ra8_i2c_msk_icsr2_stop) != 0U) {
    return k_ra8_i2c_peripheral_event_stop;
  }
  return k_ra8_i2c_peripheral_event_none;
}
 
ra8_err_t
ra8_i2c_peripheral_attach_handler(uint8_t channel, ra8_i2c_peripheral_event_fn_t fn, void* ctx)
{
  if ((uint16_t)channel >= (uint16_t)k_ra8_i2c_channel_count) {
    return k_ra8_err_invalid_arg;
  }
  s_i2c_state[channel].peripheral_handler = fn;
  s_i2c_state[channel].peripheral_ctx     = ctx;
  return k_ra8_ok;
}
 
RA8_ISR_SAFE
void ra8_i2c_peripheral_dispatch(uint8_t channel)
{
  volatile const r_i2c_regs_t* reg = ra8_i2c_regs(channel);
  if (reg == nullptr) {
    return;
  }
  if (!s_i2c_state[channel].peripheral_active) {
    return;
  }
  const ra8_i2c_peripheral_event_fn_t fn = s_i2c_state[channel].peripheral_handler;
  if (fn == nullptr) {
    return;
  }
 
  /* HUM Ch 39.2.9 "ICSR1 : I2C Bus Status Register 1" p 2382 */
  const uint8_t icsr1 = reg->ICSR1;
  /* HUM Ch 39.2.10 "ICSR2 : I2C Bus Status Register 2" p 2384 */
  const uint8_t icsr2 = reg->ICSR2;
  /* HUM Ch 39.2.2 "ICCR2 : I2C Bus Control Register 2 -- TRS" p 2371 */
  const uint8_t iccr2 = reg->ICCR2;
 
  const ra8_i2c_peripheral_event_t event = internal_i2c_dispatch_event(icsr1, icsr2, iccr2);
  if (event != k_ra8_i2c_peripheral_event_none) {
    fn(s_i2c_state[channel].peripheral_ctx, event);
  }
}