ra8_board_ek_ra8d2_ethernet.c

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#include <stddef.h>
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_board_ek_ra8d2_internal.h"
#include "ra8_cgc.h"
#include "ra8_elc_regs.h"
#include "ra8_err.h"
#include "ra8_eth.h"
#include "ra8_eth_coma.h"
#include "ra8_etha.h"
#include "ra8_etha_regs.h"
#include "ra8_gpio_constants.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_rmac.h"
#include "ra8_rmac_regs.h"
 
/* =============================================================================
 * 12. On-board RGMII Ethernet PHY (UM Table 26 + 27, page 33-34)
 * =============================================================================
 */

static const struct {
  ra8_board_eth_pin_t pin;   
  const char*         owner; 
} s_eth_routes[] = {
  {k_ra8_board_eth_pin_mdint, "ra8_board.eth.mdint"},
  {k_ra8_board_eth_pin_mdc, "ra8_board.eth.mdc"},
  {k_ra8_board_eth_pin_mdio, "ra8_board.eth.mdio"},
  {k_ra8_board_eth_pin_txd0, "ra8_board.eth.txd0"},
  {k_ra8_board_eth_pin_txd1, "ra8_board.eth.txd1"},
  {k_ra8_board_eth_pin_txd2, "ra8_board.eth.txd2"},
  {k_ra8_board_eth_pin_txd3, "ra8_board.eth.txd3"},
  {k_ra8_board_eth_pin_tx_ctl, "ra8_board.eth.tx_ctl"},
  {k_ra8_board_eth_pin_tx_clk, "ra8_board.eth.tx_clk"},
  {k_ra8_board_eth_pin_rxd0, "ra8_board.eth.rxd0"},
  {k_ra8_board_eth_pin_rxd1, "ra8_board.eth.rxd1"},
  {k_ra8_board_eth_pin_rxd2, "ra8_board.eth.rxd2"},
  {k_ra8_board_eth_pin_rxd3, "ra8_board.eth.rxd3"},
  {k_ra8_board_eth_pin_rx_ctl, "ra8_board.eth.rx_ctl"},
  {k_ra8_board_eth_pin_rx_clk, "ra8_board.eth.rx_clk"},
  {k_ra8_board_eth_pin_rstn, "ra8_board.eth.rstn"},
};

typedef enum : uint32_t {
  k_ra8_board_eth_phy_rst_low_iters  = 5000000UL,  
  k_ra8_board_eth_phy_rst_post_iters = 20000000UL, 
} ra8_board_eth_phy_reset_cycles_t;

RA8_INTERNAL static ra8_err_t internal_eth_phy_hw_reset(void)
{
  const ra8_port_pin_t rstn_pin = (ra8_port_pin_t)k_ra8_board_eth_pin_rstn;
  ra8_err_t            err      = ra8_gpio_output_init(rstn_pin, k_ra8_level_low);
  if (err != k_ra8_ok) {
    return err;
  }
  for (volatile uint32_t i = 0U; i < (uint32_t)k_ra8_board_eth_phy_rst_low_iters; ++i) {
    __asm__ volatile("nop");
  }
  err = ra8_gpio_write(rstn_pin, k_ra8_level_high);
  if (err != k_ra8_ok) {
    /* ra8_gpio_write on a valid in-range mapped port/pin always returns k_ra8_ok off-target. */
    return err; /* GCOVR_EXCL_LINE -- output_init already accepted this fixed mapped P708 pin */
  }
  for (volatile uint32_t i = 0U; i < (uint32_t)k_ra8_board_eth_phy_rst_post_iters; ++i) {
    __asm__ volatile("nop");
  }
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_err_t internal_eth_route_alt_pins(void)
{
  const ra8_port_pin_t rstn_pin = (ra8_port_pin_t)k_ra8_board_eth_pin_rstn;
  for (uint32_t i = 0U; i < sizeof(s_eth_routes) / sizeof(s_eth_routes[0]); ++i) {
    if ((ra8_port_pin_t)s_eth_routes[i].pin == rstn_pin) {
      continue;
    }
    const ra8_err_t err = ra8_pfs_route_peripheral((ra8_port_pin_t)s_eth_routes[i].pin,
                                                   k_ra8_psel_ether_rgmii,
                                                   s_eth_routes[i].owner);
    if (err != k_ra8_ok) {
      return err;
    }
  }
 
  /* RGMII transmit pins need DSCR = 01b middle drive strength. */
  /* HUM Ch 20.2.6 "PmnPFS" p 845 */
  static const uint16_t k_eth_tx_pins[] = {
    (uint16_t)k_ra8_board_eth_pin_txd0,
    (uint16_t)k_ra8_board_eth_pin_txd1,
    (uint16_t)k_ra8_board_eth_pin_txd2,
    (uint16_t)k_ra8_board_eth_pin_txd3,
    (uint16_t)k_ra8_board_eth_pin_tx_ctl,
    (uint16_t)k_ra8_board_eth_pin_tx_clk,
  };
  for (uint32_t i = 0U; i < sizeof(k_eth_tx_pins) / sizeof(k_eth_tx_pins[0]); ++i) {
    const ra8_err_t err =
      ra8_pfs_set_drive_strength((ra8_port_pin_t)k_eth_tx_pins[i], k_ra8_pfs_dscr_middle);
    if (err != k_ra8_ok) {
      /* ra8_pfs_set_drive_strength on valid mapped tx pins always returns k_ra8_ok off-target. */
      return err; /* GCOVR_EXCL_LINE -- the fixed TX-pin table contains only mapped RA8D2 pins */
    }
  }
  return k_ra8_ok;
}

typedef enum : uint32_t {
  k_ra8_board_eth_etha_step_iters = 200000UL, 
} ra8_board_eth_etha_delay_t;

RA8_PRIV ra8_err_t priv_ra8_board_eth_eswm_bring_up(uint32_t* out_eswclk_hz)
{
  ra8_err_t err = ra8_cgc_eswclk_init();
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_cgc_eswclk_hz(out_eswclk_hz);
  if (err != k_ra8_ok) {
    /* ra8_cgc_eswclk_hz only fails on nullptr; out_eswclk_hz is always a valid pointer here. */
    return err; /* GCOVR_EXCL_LINE -- nonnull out_eswclk_hz satisfies eswclk_hz's only guard */
  }
  err = ra8_mstp_enable(k_ra8_mstp_eswm);
  if (err != k_ra8_ok) {
    return err;
  }
  /* Chip-generic COMA bring-up (RRC pulse + RCEC clock fan-out + CABPIRM
   * buffer-pool init with BPR poll) now lives in the ETH HAL. */
  return ra8_eth_coma_bringup();
}

RA8_PRIV ra8_err_t priv_ra8_board_eth_etha_to_config(void)
{
  const ra8_etha_config_t etha_cfg = {
    .initial_mode = k_ra8_etha_opc_reset,
    .eaeie0_mask  = 0U,
    .eaeie1_mask  = 0U,
    .eaeie2_mask  = 0U,
  };
  ra8_err_t err = ra8_etha_init((ra8_etha_port_t)k_ra8_board_eth_etha_port, &etha_cfg);
  if (err != k_ra8_ok) {
    return err;
  }
  static const ra8_etha_opc_t k_chain[] = {
    k_ra8_etha_opc_disable,
    k_ra8_etha_opc_config,
  };
  for (uint8_t step = 0U; step < (uint8_t)(sizeof(k_chain) / sizeof(k_chain[0])); ++step) {
    err = ra8_etha_set_mode((ra8_etha_port_t)k_ra8_board_eth_etha_port, k_chain[step]);
    if (err != k_ra8_ok) {
      return err;
    }
    for (volatile uint32_t i = 0U; i < (uint32_t)k_ra8_board_eth_etha_step_iters; ++i) {
      __asm__ volatile("nop");
    }
  }
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_err_t internal_eth_etha_to_operation(void)
{
  ra8_err_t err =
    ra8_etha_set_mode((ra8_etha_port_t)k_ra8_board_eth_etha_port, k_ra8_etha_opc_operation);
  if (err != k_ra8_ok) {
    return err;
  }
  for (volatile uint32_t i = 0U; i < (uint32_t)k_ra8_board_eth_etha_step_iters; ++i) {
    __asm__ volatile("nop");
  }
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_err_t internal_eth_rmac_program(uint32_t eswclk_hz)
{
  /* HUM Ch 33.4 "MRAFC : MAC Reception Address Filter Configuration
   * Register" p 1717: each frame class has an ENABLE bit (UCENE/BCENE
   * /MCENE in the [10:0] half + matching UCENP/BCENP/MCENP in the
   * [26:16] half) AND a separate ACCEPT bit (BCACE bit 6, MCACE bit 5)
   * that controls whether the MAC actually forwards the matched frame
   * to the descriptor ring. Without BCACE the chip latches the ARP
   * broadcast in the perfect-match comparator and then drops it before
   * the GWCA agent ever sees it, so the host's ARP responder never
   * sees a "who-has 192.168.1.42" request and never replies. FSP
   * r_rmac.c::rmac_configure_reception_filter ORs both bits into the
   * canonical promiscuous mask for the same reason. */
  /* HUM Table 29.11: for an external RGMII link the RMAC's internal
   * xMII (MPIC.PIS) is MII for 10/100 Mbps and GMII for 1 Gbps -- the
   * ESWM media mux (MIICR1.MIISEL = 01b) does the RGMII conversion.
   * Default to MII (10/100 Mbps) at init so the on-chip RGMII RX
   * sample timing matches the most common PHY auto-neg outcome on
   * this board. Issue #1 bench: starting in GMII (1 Gbps) silently
   * dropped every RX frame when the PHY negotiated to 100 Mbps with
   * the Pi USB-Ethernet adapter, and the link-up-gated resync inside
   * ra8_eth_open never fired because chip-side MDIO reads of BMSR
   * return 0x0000 (the PHY's BMSR.link bit is invisible until skew
   * + clock are correct). Starting in MII makes RX work for any
   * 10/100 link the PHY auto-negotiates; for 1 Gbps links the
   * resync inside ra8_eth_link_status will promote PIS to GMII once
   * MDIO becomes usable. */
  const ra8_rmac_config_t rmac_cfg = {
    .rx_filter = (ra8_rmac_mrafc_t)(k_ra8_rmac_mrafc_unicast_match | k_ra8_rmac_mrafc_broadcast |
                                    k_ra8_rmac_mrafc_bc_accept),
    .err_irq_enable  = 0U,
    .mon0_irq_enable = 0U,
    .mon1_irq_enable = 0U,
    .mon2_irq_enable = 0U,
    .phy_interface   = k_ra8_rmac_pis_mii,
    .link_speed      = k_ra8_rmac_lsc_100mbit,
    .duplex          = k_ra8_rmac_duplex_full,
    .eswclk_hz       = eswclk_hz,
    .mdc_hz          = (uint32_t)k_ra8_rmac_mdc_default_hz,
  };
  return ra8_rmac_init((ra8_rmac_port_t)k_ra8_board_eth_rmac_port, &rmac_cfg);
}

typedef enum : uint16_t {
  k_ra8_board_eth_phy_reg_bmcr     = 0U,      
  k_ra8_board_eth_phy_reg_anar     = 4U,      
  k_ra8_board_eth_phy_reg_gbcr     = 9U,      
  k_ra8_board_eth_phy_reg_miictrl  = 0x17U,   
  k_ra8_board_eth_phy_bmcr_reset   = 0x8000U, 
  k_ra8_board_eth_phy_bmcr_an_en   = 0x1000U, 
  k_ra8_board_eth_phy_bmcr_an_rst  = 0x0200U, 
  k_ra8_board_eth_phy_rxskew_mask  = 0x7000U, 
  k_ra8_board_eth_phy_rxskew_1p0ns = 0x2000U, 
  k_ra8_board_eth_phy_anar_value   = 0x01E1U, 
  /* GBCR = 0: 1000BASE-T is not advertised, so the link settles at
   * 100M full-duplex where it runs at 0 % loss. At 1 Gbps the RGMII
   * TXC is 125 MHz DDR and the clock-to-data window shrinks to ~1 ns;
   * bench testing shows 100 % TX loss at gigabit even with the TX
   * pins at high drive (DSCR = 11b). The remaining skew lives in the
   * PEF7071's pinstrapped RGMII delay (no EEPROM is fitted, so the
   * PHY's MIICTRL skew fields are read-only) and the fixed MAC-side
   * MIICR1.TXCIDE delay -- neither is tunable in firmware. Closing
   * the gigabit eye needs a scope on the TX pins or an EEPROM to
   * override the PHY straps; until then the link stays at 100M. */
  k_ra8_board_eth_phy_gbcr_value = 0x0000U, 
  k_ra8_board_eth_phy_reset_spin = 4096U,   
} ra8_board_eth_phy_reg_t;

RA8_INTERNAL static ra8_err_t internal_eth_phy_soft_reset(void)
{
  ra8_err_t err = ra8_rmac_mdio_c22_write((ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
                                          (uint8_t)k_ra8_board_eth_phy_addr,
                                          (uint8_t)k_ra8_board_eth_phy_reg_bmcr,
                                          (uint16_t)k_ra8_board_eth_phy_bmcr_reset);
  if (err != k_ra8_ok) {
    return err;
  }
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_board_eth_phy_reset_spin; ++i) {
    uint16_t bmcr = 0U;
    err           = ra8_rmac_mdio_c22_read((ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
                                           (uint8_t)k_ra8_board_eth_phy_addr,
                                           (uint8_t)k_ra8_board_eth_phy_reg_bmcr,
                                           &bmcr);
    if (err != k_ra8_ok) {
      return err;
    }
    if ((bmcr & (uint16_t)k_ra8_board_eth_phy_bmcr_reset) == 0U) {
      return k_ra8_ok;
    }
  }
  return k_ra8_err_hw_timeout;
}

RA8_INTERNAL static ra8_err_t internal_eth_phy_set_rgmii_skew(void)
{
  uint16_t        miictrl  = 0U;
  const ra8_err_t read_err = ra8_rmac_mdio_c22_read((ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
                                                    (uint8_t)k_ra8_board_eth_phy_addr,
                                                    (uint8_t)k_ra8_board_eth_phy_reg_miictrl,
                                                    &miictrl);
  if (read_err != k_ra8_ok) {
    return read_err;
  }
  miictrl = (uint16_t)((miictrl & (uint16_t)~k_ra8_board_eth_phy_rxskew_mask) |
                       (uint16_t)k_ra8_board_eth_phy_rxskew_1p0ns);
  return ra8_rmac_mdio_c22_write((ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
                                 (uint8_t)k_ra8_board_eth_phy_addr,
                                 (uint8_t)k_ra8_board_eth_phy_reg_miictrl,
                                 miictrl);
}

RA8_INTERNAL static ra8_err_t internal_eth_phy_start_autoneg(void)
{
  ra8_err_t err = ra8_rmac_mdio_c22_write((ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
                                          (uint8_t)k_ra8_board_eth_phy_addr,
                                          (uint8_t)k_ra8_board_eth_phy_reg_anar,
                                          (uint16_t)k_ra8_board_eth_phy_anar_value);
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_rmac_mdio_c22_write((ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
                                (uint8_t)k_ra8_board_eth_phy_addr,
                                (uint8_t)k_ra8_board_eth_phy_reg_gbcr,
                                (uint16_t)k_ra8_board_eth_phy_gbcr_value);
  if (err != k_ra8_ok) {
    return err;
  }
  return ra8_rmac_mdio_c22_write(
    (ra8_rmac_port_t)k_ra8_board_eth_rmac_port,
    (uint8_t)k_ra8_board_eth_phy_addr,
    (uint8_t)k_ra8_board_eth_phy_reg_bmcr,
    (uint16_t)(k_ra8_board_eth_phy_bmcr_an_en | k_ra8_board_eth_phy_bmcr_an_rst));
}

RA8_INTERNAL static ra8_err_t internal_eth_phy_chip_init(void)
{
  ra8_err_t err = internal_eth_phy_soft_reset();
  if (err != k_ra8_ok) {
    return err;
  }
  err = internal_eth_phy_set_rgmii_skew();
  if (err != k_ra8_ok) {
    return err;
  }
  return internal_eth_phy_start_autoneg();
}
 
ra8_err_t ra8_board_ethernet_init(void)
{
  /* Step 0: hardware-reset the on-board PEF7071 PHY before anything
   * else touches MDIO. */
  ra8_err_t err = internal_eth_phy_hw_reset();
  if (err != k_ra8_ok) {
    return err;
  }
  /* Step 1: route every remaining Ethernet pin to its RGMII alt mux. */
  err = internal_eth_route_alt_pins();
  if (err != k_ra8_ok) {
    return err;
  }
  /* Step 2: bring up ESWCLK + ESWPHYCLK, release PDCTRESWM, lift the
   * ETHPHYCLK / ESWM MSTP gates, and pulse the COMA agent out of
   * reset. After this the per-port RMAC / ETHA register windows
   * answer reads and accept writes. */
  uint32_t eswclk_hz = 0U;
  err                = priv_ra8_board_eth_eswm_bring_up(&eswclk_hz);
  if (err != k_ra8_ok) {
    return err;
  }
  /* Step 3: ETHA1 RESET -> DISABLE -> CONFIG so RMAC.MPIC is writable. */
  err = priv_ra8_board_eth_etha_to_config();
  if (err != k_ra8_ok) {
    return err;
  }
  /* Step 4: select RGMII on the media-interface mux + release the
   * per-port reset, via the chip-generic ETH HAL primitive. The EK-RA8D2
   * wires its PEF7071 / GPY111 PHY to RMAC port 1 -- the canonical FSP
   * example ``ethernet_ek_ra8d2_ep`` configures every Ethernet pin as
   * ``eswm_rgmii1`` and instantiates r_rmac on Channel 1; RMAC0 / ETHA0
   * is unused on this board. ra8_eth_rgmii_select programs MIICR1 =
   * TXCIDE | RGMII and sets MIIRR.RGRST1 = 1 (HUM 29.2.1.2: an enable,
   * not an active-high reset). Without the RGRST1 enable, TXC is never
   * generated, the RMAC RX state machine is unclocked, and every RMAC RX
   * counter stays at 0 (bench-confirmed on EK-RA8D2). */
  err = ra8_eth_rgmii_select((ra8_eth_mii_port_t)k_ra8_board_eth_rmac_port);
  if (err != k_ra8_ok) {
    /* ra8_eth_rgmii_select only fails on an out-of-range port; the board
     * RMAC port constant is always valid. */
    return err; /* GCOVR_EXCL_LINE -- fixed board port 1 satisfies rgmii_select's 0..1 guard */
  }
  /* Step 5: RMAC1 bring-up. Programs MPIC (PSMCS / PIS / LSC / PIPP),
   * MAC address filter, and IRQ block. */
  err = internal_eth_rmac_program(eswclk_hz);
  if (err != k_ra8_ok) {
    return err;
  }
  /* Step 6: promote ETHA1 to OPERATION so MDIO can drive MDC. */
  err = internal_eth_etha_to_operation();
  if (err != k_ra8_ok) {
    return err;
  }
  /* Step 7: GPY111 PHY chip-init -- soft-reset, program the RGMII
   * receive-timing skew (1.0 ns), then restart auto-negotiation so
   * the link re-converges with the skew applied. Mirrors FSP
   * R_RMAC_PHY_ChipInit + R_RMAC_PHY_StartAutoNegotiate. */
  return internal_eth_phy_chip_init();
}