ra8_board_ek_ra8d2_ethernet.c File Reference

EK-RA8D2 BSP – on-board RGMII Ethernet (GPY111/PEF7071) bring-up. More...

#include <stddef.h>
#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2.h"
#include "ra8_board_ek_ra8d2_internal.h"
#include "ra8_cgc.h"
#include "ra8_elc_regs.h"
#include "ra8_err.h"
#include "ra8_eth.h"
#include "ra8_eth_coma.h"
#include "ra8_etha.h"
#include "ra8_etha_regs.h"
#include "ra8_gpio_constants.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_rmac.h"
#include "ra8_rmac_regs.h"

Include dependency graph for ra8_board_ek_ra8d2_ethernet.c:

Go to the source code of this file.

Enumerations
enum	ra8_board_eth_phy_reset_cycles_t : uint32_t {   k_ra8_board_eth_phy_rst_low_iters = 5000000UL ,   k_ra8_board_eth_phy_rst_post_iters = 20000000UL }
	Cycle-counted PHY reset timings (Cortex-M85 @ ~1 GHz). More...
enum	ra8_board_eth_etha_delay_t : uint32_t { k_ra8_board_eth_etha_step_iters = 200000UL }
	Busy-wait iteration count for the ETHA mode-walk settle delay. More...
enum	ra8_board_eth_phy_reg_t : uint16_t {   k_ra8_board_eth_phy_reg_bmcr = 0U ,   k_ra8_board_eth_phy_reg_anar = 4U ,   k_ra8_board_eth_phy_reg_gbcr = 9U ,   k_ra8_board_eth_phy_reg_miictrl = 0x17U ,   k_ra8_board_eth_phy_bmcr_reset = 0x8000U ,   k_ra8_board_eth_phy_bmcr_an_en = 0x1000U ,   k_ra8_board_eth_phy_bmcr_an_rst = 0x0200U ,   k_ra8_board_eth_phy_rxskew_mask = 0x7000U ,   k_ra8_board_eth_phy_rxskew_1p0ns = 0x2000U ,   k_ra8_board_eth_phy_anar_value = 0x01E1U ,   k_ra8_board_eth_phy_gbcr_value = 0x0000U ,   k_ra8_board_eth_phy_reset_spin = 4096U }
	GPY111 PHY register addresses + bit constants for chip-init. More...

Functions
static ra8_err_t	internal_eth_phy_hw_reset (void)
	Hardware-reset the on-board PEF7071 PHY via GPIO.
static ra8_err_t	internal_eth_route_alt_pins (void)
	Route the 15 non-RSTN ETHERC pins to their ETHERC alternate.
ra8_err_t	priv_ra8_board_eth_eswm_bring_up (uint32_t *out_eswclk_hz)
	Bring the ESWM subsystem live: clocks + power + MSTP + COMA reset.
ra8_err_t	priv_ra8_board_eth_etha_to_config (void)
	Walk ETHA1 from RESET through DISABLE to CONFIG.
static ra8_err_t	internal_eth_etha_to_operation (void)
	Promote ETHA1 from CONFIG to OPERATION (post-MPIC programming).
static ra8_err_t	internal_eth_rmac_program (uint32_t eswclk_hz)
	Programme RMAC1 with the RGMII / 1Gb full-duplex profile.
static ra8_err_t	internal_eth_phy_soft_reset (void)
	Soft-reset the GPY111 PHY and wait for the reset to clear.
static ra8_err_t	internal_eth_phy_set_rgmii_skew (void)
	Program the GPY111 RGMII receive-timing skew to 1.0 ns.
static ra8_err_t	internal_eth_phy_start_autoneg (void)
	Program the auto-neg advertisement and restart negotiation.
static ra8_err_t	internal_eth_phy_chip_init (void)
	Full GPY111 PHY chip-init: soft-reset, RX skew, restart AN.
ra8_err_t	ra8_board_ethernet_init (void)
	Bring up the on-board RGMII Ethernet PHY and RMAC1/ETHA1.

Variables
struct {
ra8_board_eth_pin_t   pin
	Pin. More...
const char *   owner
	Owner. More...
}	s_eth_routes []
	Pin table walked by ra8_board_ethernet_init.

Detailed Description

EK-RA8D2 BSP – on-board RGMII Ethernet (GPY111/PEF7071) bring-up.

Tag

[Ring 5 / BSP] {World: S}

Sibling translation unit of ra8_board_ek_ra8d2.c carrying the full on-board Ethernet bring-up sequence: PHY hardware reset, RGMII pin routing, ESWM/COMA clock + power gates, ETHA mode walk, RMAC profile programming, and the MaxLinear GPY111 (Renesas "PEF7071") PHY chip-init (soft-reset, RGMII RX skew, auto-negotiation restart). See UM Table 26

• 27 (page 33-34).

The BSP itself never touches MCU registers except for the ESWM/COMA agent windows; ra8_etha_* / ra8_rmac_* / ra8_cgc_* / ra8_mstp_* / ra8_pfs_route_peripheral carry the per-peripheral register writes. Source-of-truth for the pin tables is docs/reference/ek-ra8d2-v1-users-manual.pdf (R20UT5523EG0101 Rev 1.01, October 2025); register citations name the RA8D2 Hardware User's Manual.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file ra8_board_ek_ra8d2_ethernet.c.

Enumeration Type Documentation

ra8_board_eth_etha_delay_t

enum ra8_board_eth_etha_delay_t : uint32_t

Busy-wait iteration count for the ETHA mode-walk settle delay.

Cortex-M85 at ~1 GHz, ~3 cycles per nop. 200_000 iters is the equivalent of the FSP 1-us settle delay used between the ETHA EAMC writes (r_rmac_phy_set_operation_mode). The chip-generic COMA bring-up delays now live in ra8_eth_coma (ra8_eth_coma_bringup).

Enumerator
k_ra8_board_eth_etha_step_iters	~50 us settle between ETHA mode writes.

Definition at line 235 of file ra8_board_ek_ra8d2_ethernet.c.

ra8_board_eth_phy_reg_t

enum ra8_board_eth_phy_reg_t : uint16_t

GPY111 PHY register addresses + bit constants for chip-init.

The EK-RA8D2's on-board MaxLinear GPY111 PHY (Renesas marking "PEF7071") is brought up by mirroring FSP's R_RMAC_PHY_ChipInit + R_RMAC_PHY_StartAutoNegotiate: soft-reset the PHY, set the RGMII receive-timing skew, program the auto-negotiation advertisement, then restart auto-negotiation so the link re-converges with the skew applied. The RA8D2 ESWM MIICR1 can add only a transmit clock delay (TXCIDE); the RGMII receive delay MUST come from the PHY (MIICTRL.RXSKEW).

Enumerator
k_ra8_board_eth_phy_reg_bmcr	BMCR (basic control).
k_ra8_board_eth_phy_reg_anar	Auto-neg advertisement.
k_ra8_board_eth_phy_reg_gbcr	1000BASE-T control.
k_ra8_board_eth_phy_reg_miictrl	GPY111 MIICTRL vendor reg.
k_ra8_board_eth_phy_bmcr_reset	BMCR.RESET (self-clearing).
k_ra8_board_eth_phy_bmcr_an_en	BMCR.AUTONEG_ENABLE.
k_ra8_board_eth_phy_bmcr_an_rst	BMCR.AUTONEG_RESTART.
k_ra8_board_eth_phy_rxskew_mask	MIICTRL RXSKEW field [14:12].
k_ra8_board_eth_phy_rxskew_1p0ns	RXSKEW = 0b010 -> 1.0 ns.
k_ra8_board_eth_phy_anar_value	Advertise 100F/100H/10F/10H.
k_ra8_board_eth_phy_gbcr_value	1000BASE-T NOT advertised (see above).
k_ra8_board_eth_phy_reset_spin	BMCR.RESET self-clear cap.

Definition at line 446 of file ra8_board_ek_ra8d2_ethernet.c.

ra8_board_eth_phy_reset_cycles_t

enum ra8_board_eth_phy_reset_cycles_t : uint32_t

Cycle-counted PHY reset timings (Cortex-M85 @ ~1 GHz).

The PEF7071 datasheet sec 6.3 "Reset" requires:

• RST_N held LOW for >= 10 ms (we use >= 15 ms).
• Post-release wait >= 50 ms before any MDIO access (we use >= 60 ms).

ra8_delay_ms is NOT usable here – this function may run before global IRQs are enabled (the typical app order is setup_or_halt -> ra8_isr_globals_enable), and ra8_delay_ms is WFI + SysTick, which hangs with IRQs masked. A volatile nop loop is ~3 cycles/iter at 1 GHz so:

• 5_000_000 iters >= 15 ms
• 20_000_000 iters >= 60 ms

Enumerator
k_ra8_board_eth_phy_rst_low_iters	>= 15 ms LOW.
k_ra8_board_eth_phy_rst_post_iters	>= 60 ms HIGH.

Definition at line 103 of file ra8_board_ek_ra8d2_ethernet.c.

Function Documentation

internal_eth_etha_to_operation()

ra8_err_t internal_eth_etha_to_operation ( void )

static

Promote ETHA1 from CONFIG to OPERATION (post-MPIC programming).

MDIO transactions require ETHA in OPERATION mode (FSP r_rmac_phy_get_operation_mode invariant). Run AFTER ra8_rmac_init has programmed MPIC, never before – MPIC writes are silently dropped in any mode other than CONFIG.

Returns

k_ra8_ok on success; otherwise propagates ra8_etha_set_mode.

Return values

k_ra8_ok	ETHA promoted to OPERATION.
k_ra8_err_invalid_arg	ra8_etha_set_mode rejected an argument.

Precondition

ra8_rmac_init has programmed RMAC1 MPIC.

Single-threaded init context.

Postcondition

ETHA1 EAMC = OPERATION; subsequent ra8_rmac_mdio_c22_read works.

Busy-wait gives the EAMC write time to take effect.

Note

Not thread-safe.

Since

0.1.0

Definition at line 355 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_etha_port, k_ra8_board_eth_etha_step_iters, k_ra8_etha_opc_operation, k_ra8_ok, ra8_etha_set_mode(), and RA8_INTERNAL.

Referenced by ra8_board_ethernet_init().

internal_eth_phy_chip_init()

ra8_err_t internal_eth_phy_chip_init ( void )

static

Full GPY111 PHY chip-init: soft-reset, RX skew, restart AN.

Sequences the three FSP-equivalent PHY bring-up steps so ra8_board_ethernet_init stays under the function-size cap.

Returns

ra8_err_t Error code from the first failing sub-step.

Return values

k_ra8_ok	PHY initialised, auto-neg restarted.
k_ra8_err_hw_timeout	An MDIO transaction or reset timed out.

Precondition

ETHA1 is in OPERATION mode; RMAC1 MPIC.PSMCS != 0.

The PHY has had its hardware (RSTN) reset.

Postcondition

GPY111 RGMII RX skew = 1.0 ns and auto-neg is re-running.

The link will re-converge with the corrected RGMII timing.

Note

Not thread-safe.

Since

0.1.0

Definition at line 613 of file ra8_board_ek_ra8d2_ethernet.c.

References internal_eth_phy_set_rgmii_skew(), internal_eth_phy_soft_reset(), internal_eth_phy_start_autoneg(), k_ra8_ok, and RA8_INTERNAL.

Referenced by ra8_board_ethernet_init().

internal_eth_phy_hw_reset()

ra8_err_t internal_eth_phy_hw_reset ( void )

static

Hardware-reset the on-board PEF7071 PHY via GPIO.

Routes the board's PHY_RSTN net (P708) as a plain GPIO output, asserts LOW for the required hold time, releases HIGH, and leaves the pin in GPIO mode driven HIGH for the rest of the application. The ETHERC alternate mux does NOT source RSTN, so the pin MUST stay a GPIO to keep the PHY out of reset.

Returns

Result code.

Return values

k_ra8_ok	PHY reset cycle completed.
k_ra8_err_invalid_arg	GPIO init / write rejected.

Precondition

RA8D2 IOPORT clock is on (chip-default reset state is fine).

Caller serialises (single-threaded init context).

Postcondition

P708 is in GPIO-output mode driven HIGH.

>= 60 ms has elapsed since RST_N rising edge.

Note

Not thread-safe.

Since

0.1.0

Definition at line 130 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_phy_rst_low_iters, k_ra8_board_eth_phy_rst_post_iters, k_ra8_board_eth_pin_rstn, k_ra8_level_high, k_ra8_level_low, k_ra8_ok, ra8_gpio_output_init(), ra8_gpio_write(), and RA8_INTERNAL.

Referenced by ra8_board_ethernet_init().

internal_eth_phy_set_rgmii_skew()

ra8_err_t internal_eth_phy_set_rgmii_skew ( void )

static

Program the GPY111 RGMII receive-timing skew to 1.0 ns.

Read-modify-write of MIICTRL (vendor reg 0x17): clears the RXSKEW field (bits 14:12), sets it to 0b010 = 1.0 ns. Mirrors FSP rmac_phy_target_gpy111_initialize.

Returns

ra8_err_t Error code.

Return values

k_ra8_ok	RXSKEW programmed to 1.0 ns.
k_ra8_err_hw_timeout	An MDIO transaction timed out.

Precondition

ETHA1 is in OPERATION mode.

internal_eth_phy_soft_reset has completed.

Postcondition

GPY111 MIICTRL.RXSKEW == 0b010 (1.0 ns).

No other MIICTRL bits are disturbed.

Note

Not thread-safe.

Since

0.1.0

Definition at line 533 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_phy_addr, k_ra8_board_eth_phy_reg_miictrl, k_ra8_board_eth_phy_rxskew_1p0ns, k_ra8_board_eth_phy_rxskew_mask, k_ra8_board_eth_rmac_port, k_ra8_ok, RA8_INTERNAL, ra8_rmac_mdio_c22_read(), and ra8_rmac_mdio_c22_write().

Referenced by internal_eth_phy_chip_init().

internal_eth_phy_soft_reset()

ra8_err_t internal_eth_phy_soft_reset ( void )

static

Soft-reset the GPY111 PHY and wait for the reset to clear.

Mirrors the soft-reset step in FSP R_RMAC_PHY_ChipInit: write BMCR.RESET, poll BMCR until the bit self-clears.

Returns

ra8_err_t Error code.

Return values

k_ra8_ok	PHY reset completed.
k_ra8_err_hw_timeout	BMCR.RESET never self-cleared.

Precondition

ETHA1 is in OPERATION mode (MDIO can drive MDC).

RMAC1 MPIC.PSMCS is non-zero.

Postcondition

The PHY has completed a register-level soft reset.

BMCR.RESET reads 0.

Note

Not thread-safe.

Since

0.1.0

Definition at line 489 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_phy_addr, k_ra8_board_eth_phy_bmcr_reset, k_ra8_board_eth_phy_reg_bmcr, k_ra8_board_eth_phy_reset_spin, k_ra8_board_eth_rmac_port, k_ra8_err_hw_timeout, k_ra8_ok, RA8_INTERNAL, ra8_rmac_mdio_c22_read(), and ra8_rmac_mdio_c22_write().

Referenced by internal_eth_phy_chip_init().

internal_eth_phy_start_autoneg()

ra8_err_t internal_eth_phy_start_autoneg ( void )

static

Program the auto-neg advertisement and restart negotiation.

Mirrors FSP R_RMAC_PHY_StartAutoNegotiate: writes ANAR (10/100 abilities + selector), GBCR (1000BASE-T abilities), then BMCR = AUTONEG_ENABLE | AUTONEG_RESTART. The restart forces the GPY111 to re-converge the link AFTER the RGMII RX skew has been applied, so the running link uses the corrected timing.

Returns

ra8_err_t Error code.

Return values

k_ra8_ok	Advertisement programmed, AN restarted.
k_ra8_err_hw_timeout	An MDIO transaction timed out.

Precondition

internal_eth_phy_set_rgmii_skew has completed.

ETHA1 is in OPERATION mode.

Postcondition

ANAR / GBCR hold the advertised abilities.

Auto-negotiation has been restarted.

Note

Not thread-safe.

Since

0.1.0

Definition at line 572 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_phy_addr, k_ra8_board_eth_phy_anar_value, k_ra8_board_eth_phy_bmcr_an_en, k_ra8_board_eth_phy_bmcr_an_rst, k_ra8_board_eth_phy_gbcr_value, k_ra8_board_eth_phy_reg_anar, k_ra8_board_eth_phy_reg_bmcr, k_ra8_board_eth_phy_reg_gbcr, k_ra8_board_eth_rmac_port, k_ra8_ok, RA8_INTERNAL, and ra8_rmac_mdio_c22_write().

Referenced by internal_eth_phy_chip_init().

internal_eth_rmac_program()

ra8_err_t internal_eth_rmac_program ( uint32_t eswclk_hz )

static

Programme RMAC1 with the RGMII / 1Gb full-duplex profile.

ra8_rmac_init is the API that lands MPIC; this helper builds the RGMII config struct and hands it off so the bring-up function below stays under the function-size threshold.

Parameters

[in]

eswclk_hz

Live ESWCLK frequency in Hz (from priv_ra8_board_eth_eswm_bring_up).

Returns

k_ra8_ok on success; otherwise propagates ra8_rmac_init.

Return values

k_ra8_ok	RMAC1 initialised.
k_ra8_err_invalid_arg	ra8_rmac_init rejected the cfg block.

Precondition

ETHA1 is in CONFIG mode (::internal_eth_etha_to_config has run).

eswclk_hz > 0.

Postcondition

RMAC1 MPIC programmed for RGMII / 1Gb / full / 1 MHz MDC.

MAC address filter set to unicast + broadcast accept.

Note

Not thread-safe.

Since

0.1.0

Definition at line 389 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_rmac_port, k_ra8_rmac_duplex_full, k_ra8_rmac_lsc_100mbit, k_ra8_rmac_mdc_default_hz, k_ra8_rmac_mrafc_bc_accept, k_ra8_rmac_mrafc_broadcast, k_ra8_rmac_mrafc_unicast_match, k_ra8_rmac_pis_mii, RA8_INTERNAL, and ra8_rmac_init().

Referenced by ra8_board_ethernet_init().

internal_eth_route_alt_pins()

ra8_err_t internal_eth_route_alt_pins ( void )

static

Route the 15 non-RSTN ETHERC pins to their ETHERC alternate.

Walks s_eth_routes and assigns every pin EXCEPT RSTN to the RGMII PSEL slot. The EK-RA8D2 wires its PEF7071 / GPY111 PHY in RGMII mode (data pins: 4xTXD + 4xRXD + TXC + RXC + TX_CTL + RX_CTL plus MDC / MDIO / MDINT / RSTN) – the FSP config.xml for the canonical ethernet_ek_ra8d2_ep example routes every Ethernet pin via the eswm_rgmii1 PSEL, which corresponds to k_ra8_psel_ether_rgmii (PSEL field value 0x18, comment "PDC / AGT1 / Ether RGMII" in libs/ra8_hal/inc/ra8_mpc.h).

After routing, the six RGMII transmit pins (TXD0..3, TX_CTL, TX_CLK) get their PmnPFS.DSCR bumped from the reset-default low drive to middle drive. HUM Ch 20.2.6 mandates DSCR = 01b for an RGMII/3.3 V transmit pin; leaving it at 00b is an unsupported combination – bench-confirmed on EK-RA8D2 to corrupt ~70 % of transmitted frames at 100 Mbps and 100 % at 1 Gbps (the receive pins are inputs, so their drive strength is irrelevant and they are left at the default). The on-board PEF7071 runs its MII rail at 3.3 V (MIICTRL.V25_33 strap = 0), hence the 3.3 V row of the HUM table -> k_ra8_pfs_dscr_middle.

Returns

Result code from ra8_pfs_route_peripheral.

Return values

k_ra8_ok	All 15 alt-function pins routed.
k_ra8_err_invalid_arg	ra8_pfs_route_peripheral rejected one pin.

Precondition

internal_eth_phy_hw_reset has run.

PFS write-protect is unlocked by ra8_pfs_route_peripheral.

Postcondition

15 pins (MDC/MDIO/TXDx/RXDx/TX_CTL/RX_CTL/TXCLK/RXCLK/MDINT) are routed to the RGMII ETHERC alternate.

The six RGMII transmit pins are at DSCR = middle drive.

RSTN stays a GPIO (never touched here).

Note

Not thread-safe.

Since

0.1.0

Definition at line 189 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_pin_rstn, k_ra8_board_eth_pin_tx_clk, k_ra8_board_eth_pin_tx_ctl, k_ra8_board_eth_pin_txd0, k_ra8_board_eth_pin_txd1, k_ra8_board_eth_pin_txd2, k_ra8_board_eth_pin_txd3, k_ra8_ok, k_ra8_pfs_dscr_middle, k_ra8_psel_ether_rgmii, owner, pin, RA8_INTERNAL, ra8_pfs_route_peripheral(), ra8_pfs_set_drive_strength(), and s_eth_routes.

Referenced by ra8_board_ethernet_init().

priv_ra8_board_eth_eswm_bring_up()

ra8_err_t priv_ra8_board_eth_eswm_bring_up

(

uint32_t *

out_eswclk_hz

)

Bring the ESWM subsystem live: clocks + power + MSTP + COMA reset.

Bring up the Ethernet clock, power, MSTP, and COMA boundary.

Factored out of ra8_board_ethernet_init to keep that function under the project's NASA Rule 4 / clang-tidy function-size threshold. Runs the four upstream gates the RMAC / ETHA register windows hang off: ESWCLK / ESWPHYCLK, PDCTRESWM power-on, MSTPC30 (ESWM) MSTP release, MSTPC28 (ETHPHYCLK) MSTP release, and finally the chip-generic COMA RRC/RCEC/CABPIRM bring-up via ra8_eth_coma_bringup. out_eswclk_hz receives the live ESWCLK frequency so the caller can plumb it into ra8_rmac_config_t.

Parameters

[out]

out_eswclk_hz

Live ESWCLK frequency in Hz on success.

Returns

Error code from the underlying CGC / MSTP / COMA paths.

Return values

k_ra8_ok	Bring-up sequence completed.
k_ra8_err_hw_timeout	Sub-step (eswclk, MSTP) timed out.

Precondition

out_eswclk_hz is a valid 32-bit pointer.

Single-threaded init context.

Postcondition

On k_ra8_ok, ESWM is fully clocked + COMA is out of reset.

*out_eswclk_hz holds the live ESWCLK frequency.

Note

Not thread-safe.

Since

0.1.0

Definition at line 265 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_mstp_eswm, k_ra8_ok, ra8_cgc_eswclk_hz(), ra8_cgc_eswclk_init(), ra8_eth_coma_bringup(), ra8_mstp_enable(), and RA8_PRIV.

Referenced by ra8_board_ethernet_init().

priv_ra8_board_eth_etha_to_config()

ra8_err_t priv_ra8_board_eth_etha_to_config

(

void

)

Walk ETHA1 from RESET through DISABLE to CONFIG.

Walk the board Ethernet ETHA from RESET to CONFIG.

Per FSP r_rmac_phy_open, RMAC.MPIC is only writable while the paired ETHA is in CONFIG mode (writes are silently dropped in other modes). This helper drives ETHA into CONFIG so ra8_rmac_init can land the MPIC programming; internal_eth_etha_to_operation flips to OPERATION afterwards so MDIO traffic can start.

Returns

k_ra8_ok on success; otherwise propagates ra8_etha_set_mode.

Return values

k_ra8_ok	Walked to CONFIG.
k_ra8_err_invalid_arg	ra8_etha_set_mode rejected an argument.

Precondition

priv_ra8_board_eth_eswm_bring_up has succeeded.

Single-threaded init context.

Postcondition

ETHA1 EAMC reflects CONFIG; busy-wait between writes mirrors FSP r_rmac_phy_set_operation_mode.

EAMS.OPS == CONFIG (best-effort; FSP does not poll either).

Note

Not thread-safe.

Since

0.1.0

Definition at line 307 of file ra8_board_ek_ra8d2_ethernet.c.

References k_ra8_board_eth_etha_port, k_ra8_board_eth_etha_step_iters, k_ra8_etha_opc_config, k_ra8_etha_opc_disable, k_ra8_etha_opc_reset, k_ra8_ok, ra8_etha_init(), ra8_etha_set_mode(), and RA8_PRIV.

Referenced by ra8_board_ethernet_init().

ra8_board_ethernet_init()

ra8_err_t ra8_board_ethernet_init

(

void

)

Bring up the on-board RGMII Ethernet PHY and RMAC1/ETHA1.

Hardware-resets the PEF7071/GPY111 through RSTN (P708), leaving that signal as a GPIO output driven high. The other 15 Ethernet signals are routed to their RGMII alternate functions before the ESWM clocks, power, module-stop gates, and COMA buffer pool are brought up. ETHA1 then walks RESET to CONFIG, the external media mux selects RGMII, and RMAC1 starts with its internal xMII profile at MII, 100 Mbps, full duplex.

After RMAC1 programming, ETHA1 enters OPERATION and this function soft-resets the PHY, applies the RGMII receive skew, advertises the supported 10/100 modes, and restarts PHY auto-negotiation internally.

Returns

ra8_err_t Result from the first failing Ethernet bring-up stage.

Return values

k_ra8_ok	Bring-up completed and PHY auto-negotiation restarted.
k_ra8_err_gpio_conflict	RSTN or an alternate-function pin is owned.
k_ra8_err_invalid_state	An Ethernet module-stop reference is saturated.
k_ra8_err_hw_timeout	A clock, module-stop, ETHA, COMA, or MDIO wait timed out.

Precondition

IOPORT module powered (reset default).

ra8_mstp_init() has run.

Postcondition

Fifteen Ethernet pins use the RGMII alternate; RSTN remains GPIO-high.

RMAC1 and ETHA1 are operational and PHY auto-negotiation is running.

Note

Not thread-safe; call once during board bring-up.

Since

0.1.0

Definition at line 626 of file ra8_board_ek_ra8d2_ethernet.c.

References internal_eth_etha_to_operation(), internal_eth_phy_chip_init(), internal_eth_phy_hw_reset(), internal_eth_rmac_program(), internal_eth_route_alt_pins(), k_ra8_board_eth_rmac_port, k_ra8_ok, priv_ra8_board_eth_eswm_bring_up(), priv_ra8_board_eth_etha_to_config(), and ra8_eth_rgmii_select().

Referenced by demo_setup_or_halt(), eop_run_once(), and internal_demo_setup_or_halt().

Variable Documentation

owner

const char* owner

Owner.

Definition at line 66 of file ra8_board_ek_ra8d2_ethernet.c.

Referenced by internal_audio_route_pins(), internal_eth_route_alt_pins(), internal_init_bind_owner(), internal_init_setup_ep0(), internal_state_for(), ra8_pfs_route_peripheral(), and ra8_pin_validator_claim().

pin

ra8_board_eth_pin_t pin

Pin.

Definition at line 65 of file ra8_board_ek_ra8d2_ethernet.c.

Referenced by board_periph_gpio_get_input(), board_periph_gpio_set_input(), c6_hosted_print_pin(), c6_hosted_print_route(), cam_claim_probe_pins(), cam_release_probe_pins(), er_sw_pressed(), internal_attach_hardware(), internal_audio_route_pins(), internal_capture_xspi_pin_state(), internal_check(), internal_claim(), internal_config_gpio(), internal_config_gpio_as_interrupt(), internal_cs_try(), internal_dly_cell(), internal_eth_route_alt_pins(), internal_find(), internal_flat_index(), internal_glcdc_force_pin_output(), internal_hold_gpio(), internal_irq_find(), internal_kick_net(), internal_main_apply_button_battery(), internal_pin_if_output_init(), internal_pin_if_read(), internal_pin_if_toggle(), internal_pin_if_write(), internal_pin_in_range(), internal_port_trace_leds(), internal_pull_gpio(), internal_pull_read(), internal_ra8_epaper_pulse_reset(), internal_ra8_epaper_wait_ready(), internal_read_gpio(), internal_reset_pfs(), internal_sample(), internal_teardown_gpio_interrupt(), internal_update_pfs(), internal_validate_slot(), internal_write_gpio(), priv_ra8_esp_hosted_gpio_edge_register(), priv_ra8_esp_hosted_gpio_edge_unregister(), ra8_board_arduino_gpio_read(), ra8_board_arduino_gpio_write(), ra8_board_arduino_pin_init(), ra8_board_glcdc_init(), ra8_board_led_init(), ra8_board_led_off(), ra8_board_led_on(), ra8_board_led_toggle(), ra8_board_sw_init(), ra8_board_sw_read(), ra8_cache_store_pin(), ra8_esp_hosted_pin_irq_num(), ra8_gpio_attach_irq(), ra8_gpio_detach_irq(), ra8_gpio_input_init(), ra8_gpio_output_init(), ra8_gpio_read(), ra8_gpio_release(), ra8_gpio_toggle(), ra8_gpio_write(), ra8_gpt_duty_cycle_set(), ra8_gpt_pwm_pin_configure(), ra8_mpc_read_pfs(), ra8_mpc_route_peripheral(), ra8_mpc_set_analog(), ra8_mpc_set_gpio(), ra8_mpc_set_irq(), ra8_mpc_set_open_drain(), ra8_mpc_set_pull(), ra8_pcntr_read(), ra8_pcntr_set_output(), ra8_pdg_get_delay(), ra8_pdg_pin_disable(), ra8_pdg_set_delay(), ra8_pdg_set_delay_batch(), ra8_pfs_pmn(), ra8_pfs_route_peripheral(), ra8_pfs_set_drive_strength(), ra8_pin_validator_claim(), ra8_pin_validator_is_claimed(), ra8_pin_validator_release(), set_switch(), and wd_sw_pressed().

[struct]

const struct { ... } s_eth_routes[]

Initial value:

= {
  {k_ra8_board_eth_pin_mdint, "ra8_board.eth.mdint"},
  {k_ra8_board_eth_pin_mdc, "ra8_board.eth.mdc"},
  {k_ra8_board_eth_pin_mdio, "ra8_board.eth.mdio"},
  {k_ra8_board_eth_pin_txd0, "ra8_board.eth.txd0"},
  {k_ra8_board_eth_pin_txd1, "ra8_board.eth.txd1"},
  {k_ra8_board_eth_pin_txd2, "ra8_board.eth.txd2"},
  {k_ra8_board_eth_pin_txd3, "ra8_board.eth.txd3"},
  {k_ra8_board_eth_pin_tx_ctl, "ra8_board.eth.tx_ctl"},
  {k_ra8_board_eth_pin_tx_clk, "ra8_board.eth.tx_clk"},
  {k_ra8_board_eth_pin_rxd0, "ra8_board.eth.rxd0"},
  {k_ra8_board_eth_pin_rxd1, "ra8_board.eth.rxd1"},
  {k_ra8_board_eth_pin_rxd2, "ra8_board.eth.rxd2"},
  {k_ra8_board_eth_pin_rxd3, "ra8_board.eth.rxd3"},
  {k_ra8_board_eth_pin_rx_ctl, "ra8_board.eth.rx_ctl"},
  {k_ra8_board_eth_pin_rx_clk, "ra8_board.eth.rx_clk"},
  {k_ra8_board_eth_pin_rstn, "ra8_board.eth.rstn"},
}

Pin table walked by ra8_board_ethernet_init.

Every entry is one of the sixteen Ethernet signals from UM Table 26 p 33. All sixteen need k_ra8_psel_ether_rmii (the RA8D2 PSEL slot 0x11 covers both RMII and RGMII – the per-pin mux is the same; the RMAC.MPIC.PIS field selects RGMII vs RMII for the data path).

Referenced by internal_eth_route_alt_pins().