ra8_esp_hosted_port.c

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#include "ra8_esp_hosted_port.h"
 
#include <stdint.h>
 
#include "esp_hosted_os_abstraction.h"
#include "port_esp_hosted_host_config.h"
#include "port_esp_hosted_host_log.h"
#include "port_esp_hosted_host_os.h"
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_esp_hosted_gpio_internal.h"
#include "ra8_esp_hosted_osi_internal.h"
#include "ra8_esp_hosted_pins.h"
#include "ra8_esp_hosted_port_internal.h"
#include "ra8_esp_hosted_rtos_internal.h"
#include "ra8_esp_hosted_spi_internal.h"
#include "ra8_port_constants.h"
 
DEFINE_LOG_TAG(port);

typedef enum : uint8_t {
  k_ra8_esp_hosted_port_sci_channels = 10U,
} ra8_esp_hosted_port_limit_t;

static bool s_ra8_esp_hosted_port_ready;

RA8_PRIV
ra8_err_t priv_ra8_esp_hosted_port_cfg_check(const ra8_esp_hosted_port_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_esp_hosted_tag, "cfg");
 
  if (cfg->pclk_hz == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (cfg->sck_hz == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (cfg->edge_poll_ms == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (cfg->sci_channel >= (uint8_t)k_ra8_esp_hosted_port_sci_channels) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL
static bool internal_pin_in_range(uint16_t pin)
{
  return ((uint16_t)RA8_PIN_PORT(pin) <= (uint16_t)k_ra8_port_max) &&
         ((uint16_t)RA8_PIN_PIN(pin) <= (uint16_t)k_ra8_pin_max);
}

RA8_PRIV
ra8_err_t priv_ra8_esp_hosted_port_pins_check_values(uint16_t chip_select,
                                                     uint16_t handshake,
                                                     uint16_t data_ready)
{
  if ((chip_select == handshake) || (chip_select == data_ready) || (handshake == data_ready)) {
    return k_ra8_err_invalid_arg;
  }
  if (!internal_pin_in_range(chip_select)) {
    return k_ra8_err_invalid_arg;
  }
  if (!internal_pin_in_range(handshake)) {
    return k_ra8_err_invalid_arg;
  }
  if (!internal_pin_in_range(data_ready)) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_PRIV
ra8_err_t priv_ra8_esp_hosted_port_pins_check(void)
{
  return priv_ra8_esp_hosted_port_pins_check_values((uint16_t)k_ra8_esp_hosted_pin_chip_select,
                                                    (uint16_t)k_ra8_esp_hosted_pin_handshake,
                                                    (uint16_t)k_ra8_esp_hosted_pin_data_ready);
}

RA8_INTERNAL
static ra8_err_t internal_configure_sideband(void)
{
  if (g_h.funcs->_h_config_gpio(H_GPIO_HANDSHAKE_Port,
                                (uint32_t)H_GPIO_HANDSHAKE_Pin,
                                H_GPIO_MODE_DEF_INPUT) != RET_OK) {
    ESP_LOGE(s_esp_hosted_tag, "handshake pin would not configure as an input");
    return k_ra8_err_gpio_conflict;
  }
  if (g_h.funcs->_h_config_gpio(H_GPIO_DATA_READY_Port,
                                (uint32_t)H_GPIO_DATA_READY_Pin,
                                H_GPIO_MODE_DEF_INPUT) != RET_OK) {
    ESP_LOGE(s_esp_hosted_tag, "data-ready pin would not configure as an input");
    return k_ra8_err_gpio_conflict;
  }
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_unwind(void)
{
  /* Both release steps run before either result is folded, so neither can be
     skipped by an earlier failure. The fold itself lives in
     `priv_ra8_esp_hosted_port_first_error()` because it is the only decision here
     and reaching this function needs a brought-up port. */
  const ra8_err_t spi_err  = priv_ra8_esp_hosted_spi_close();
  ra8_err_t       first    = priv_ra8_esp_hosted_port_first_error(k_ra8_ok, spi_err);
  const ra8_err_t rtos_err = priv_ra8_esp_hosted_rtos_deinit();
  first                    = priv_ra8_esp_hosted_port_first_error(first, rtos_err);
 
  g_hosted_osi_funcs          = (hosted_osi_funcs_t){};
  s_ra8_esp_hosted_port_ready = false;
  return first;
}

RA8_PRIV
ra8_err_t priv_ra8_esp_hosted_port_first_error(ra8_err_t first, ra8_err_t next)
{
  if ((first == k_ra8_ok) && (next != k_ra8_ok)) {
    return next;
  }
  return first;
}

RA8_INTERNAL
static ra8_err_t internal_bring_up(const ra8_esp_hosted_port_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_esp_hosted_tag, "cfg");
 
  ra8_err_t err = priv_ra8_esp_hosted_rtos_init();
  if (err != k_ra8_ok) {
    return err;
  }
 
  err = priv_ra8_esp_hosted_osi_bind_all(&g_hosted_osi_funcs);
  if (err == k_ra8_ok) {
    err = priv_ra8_esp_hosted_gpio_set_edge_poll_ms(cfg->edge_poll_ms);
  }
  if (err == k_ra8_ok) {
    err = priv_ra8_esp_hosted_spi_open(cfg->sci_channel, cfg->pclk_hz, cfg->sck_hz);
  }
  if (err == k_ra8_ok) {
    err = internal_configure_sideband();
  }
  return err;
}

ra8_err_t ra8_esp_hosted_port_init(const ra8_esp_hosted_port_cfg_t* cfg)
{
  const ra8_err_t cfg_err = priv_ra8_esp_hosted_port_cfg_check(cfg);
  if (cfg_err != k_ra8_ok) {
    return cfg_err;
  }
  if (s_ra8_esp_hosted_port_ready) {
    return k_ra8_err_invalid_state;
  }
 
  const ra8_err_t pin_err = priv_ra8_esp_hosted_port_pins_check();
  if (pin_err != k_ra8_ok) {
    ESP_LOGE(s_esp_hosted_tag, "pin map is not self-consistent");
    return pin_err;
  }
 
  const ra8_err_t err = internal_bring_up(cfg);
  if (err != k_ra8_ok) {
    (void)internal_unwind();
    return err;
  }
 
  s_ra8_esp_hosted_port_ready = true;
  ESP_LOGI(s_esp_hosted_tag,
           "esp-hosted port up on SCI%u at %u Hz",
           (unsigned int)cfg->sci_channel,
           (unsigned int)cfg->sck_hz);
  return k_ra8_ok;
}

ra8_err_t ra8_esp_hosted_port_deinit(void)
{
  if (!s_ra8_esp_hosted_port_ready) {
    return k_ra8_err_not_initialized;
  }
  return internal_unwind();
}

bool ra8_esp_hosted_port_is_ready(void)
{
  return s_ra8_esp_hosted_port_ready;
}
 
bool ra8_esp_hosted_port_rx_pending(void)
{
  if (!s_ra8_esp_hosted_port_ready) {
    return false;
  }
  const int level =
    g_h.funcs->_h_read_gpio(H_GPIO_DATA_READY_Port, (uint32_t)H_GPIO_DATA_READY_Pin);
  return level == H_DR_VAL_ACTIVE;
}