port_esp_hosted_host_config.h File Reference

esp-hosted port header: transport selection, side-band pin map, link polarity. More...

#include <stdint.h>
#include "ra8_esp_hosted_pins.h"
#include "port_esp_hosted_host_config_features.h"
#include "port_esp_hosted_host_config_transports.h"

Include dependency graph for port_esp_hosted_host_config.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros
#define	H_TRANSPORT_NONE   (0)
	No transport has been configured yet.
#define	H_TRANSPORT_SPI   (1)
	Transport id of the full-duplex SPI link.
#define	H_TRANSPORT_SDIO   (2)
	Transport id of the SDIO link.
#define	H_TRANSPORT_SPI_HD   (3)
	Transport id of the half-duplex (1/2/4-line) SPI link.
#define	H_TRANSPORT_UART   (4)
	Transport id of the UART link.
#define	H_TRANSPORT_IN_USE   (H_TRANSPORT_SPI)
	The transport this image actually drives.
#define	H_SLAVE_TARGET_ESP32C6   (1) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor on this board is an ESP32-C6.
#define	H_SLAVE_TARGET_ESP32   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an original ESP32.
#define	H_SLAVE_TARGET_ESP32C2   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-C2.
#define	H_SLAVE_TARGET_ESP32C3   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-C3.
#define	H_SLAVE_TARGET_ESP32C5   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-C5.
#define	H_SLAVE_TARGET_ESP32C61   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-C61.
#define	H_SLAVE_TARGET_ESP32H2   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-H2.
#define	H_SLAVE_TARGET_ESP32H4   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-H4.
#define	H_SLAVE_TARGET_ESP32S2   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-S2.
#define	H_SLAVE_TARGET_ESP32S3   (0) /* LEGACY-OK: upstream esp-hosted macro name */
	The co-processor is not an ESP32-S3.
#define	RA8_ESP_HOSTED_GPIO_PORT(pin_code)
	Extract the void* port half of a packed RA8 pin.
#define	RA8_ESP_HOSTED_GPIO_PIN(pin_code)
	Extract the int pin half of a packed RA8 pin, or -1 if unwired.
#define	H_GPIO_HANDSHAKE_Port   RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_handshake)
	Opaque port handle of the HANDSHAKE input.
#define	H_GPIO_HANDSHAKE_Pin   RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_handshake)
	Pin index of the HANDSHAKE input, or -1 when it is not wired.
#define	H_GPIO_DATA_READY_Port   RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_data_ready)
	Opaque port handle of the DATA_READY input.
#define	H_GPIO_DATA_READY_Pin   RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_data_ready)
	Pin index of the DATA_READY input, or -1 when it is not wired.
#define	H_GPIO_PORT_RESET   RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_reset)
	Opaque port handle of the co-processor reset output.
#define	H_GPIO_PIN_RESET   RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_reset)
	Pin index of the co-processor reset output, or -1 when unwired.
#define	H_HANDSHAKE_ACTIVE_HIGH   (1)
	Whether the co-processor asserts HANDSHAKE by driving it high.
#define	H_DATAREADY_ACTIVE_HIGH   (1)
	Whether the co-processor asserts DATA_READY by driving it high.
#define	H_HS_VAL_ACTIVE   (1)
	Level read back on HANDSHAKE when it is asserted.
#define	H_HS_VAL_INACTIVE   (0)
	Level read back on HANDSHAKE when it is deasserted.
#define	H_HS_INTR_EDGE   (1)
	Interrupt sense the port programs for the HANDSHAKE input.
#define	H_DR_VAL_ACTIVE   (1)
	Level read back on DATA_READY when a frame is waiting.
#define	H_DR_VAL_INACTIVE   (0)
	Level read back on DATA_READY when nothing is waiting.
#define	H_DR_INTR_EDGE   (1)
	Interrupt sense the port programs for the DATA_READY input.
#define	H_RESET_VAL_ACTIVE   (0)
	Level that holds the co-processor in reset.
#define	H_RESET_VAL_INACTIVE   (1)
	Level that releases the co-processor from reset.
#define	H_TRANSPORT_QUEUE_SIZE   (20)
	Frames a single transport direction can hold.
#define	H_ESP_HOSTED_HOST   (1)
	Marks this build as the esp-hosted host, not the co-processor.
#define	H_ESP_PAYLOAD_HEADER_OFFSET   (12)
	Bytes of esp-hosted payload header in front of every frame.
#define	H_SPI_FD_CLK_MHZ   (5)
	Full-duplex SPI clock, in megahertz.
#define	H_ENABLE   (1)
	Generic "switch this on" argument for the GPIO vtable.
#define	H_DISABLE   (0)
	Generic "switch this off" argument for the GPIO vtable.

Detailed Description

esp-hosted port header: transport selection, side-band pin map, link polarity.

Tag

[Ring 4 / PORT] {World: NS}

The most widely reached of the ten port headers the vendored esp-hosted core includes by name (see docs/SOUP/esp-hosted-host.md): nineteen vendored translation units name it, either directly or through transport_drv.h. Upstream generates its equivalent from Kconfig under host/port/, which this project excludes; this file is its first-party replacement and therefore keeps the upstream file name and every upstream macro spelling exactly.

What lives here and what does not

This header answers "which transport, on which wires, with what polarity". Three neighbours own the rest, and none of the four ever defines the same symbol twice:

• port_esp_hosted_host_config_transports.h – the SDIO, half-duplex SPI and UART blocks. Those transports are not in use, but their drivers still compile, so their constants must exist.
• port_esp_hosted_host_config_features.h – host features this port does not implement, the RPC bounds and the debug counters.
• port_esp_hosted_host_wifi_config.h – Wi-Fi and supplicant feature availability, which tracks the co-processor image rather than the board. Both sibling config headers are included from the bottom of this file, so a translation unit that names only the upstream file gets the complete set, and the #if derivations in them see the polarity flags defined here.

The GPIO encoding contract

The vendored core moves side-band pins around as an opaque void* port plus an int pin (gpio_pin_t in esp_hosted_transport_config.h). This port encodes an RA8 pin into that pair with RA8_ESP_HOSTED_GPIO_PORT and RA8_ESP_HOSTED_GPIO_PIN, which split the packed ra8_port_pin_t from ra8_esp_hosted_pins.h using RA8_PIN_PORT() / RA8_PIN_PIN():

• the ..._Port value is the port index cast to void*, so port 0 encodes as a null pointer. That is legal here because the port never null-checks the port argument – it range-checks the decoded index, and index 0 is a real RA8 port;
• the ..._Pin value is the pin index within that port, or -1 when the pin is k_ra8_pin_none. Minus one is the vendored code's own "not wired" spelling: spi_drv.c tests != -1 before it configures or tears down a side-band interrupt. Every pin fact stays in ra8_esp_hosted_pins.h; nothing here restates a port or pin number.

Interrupt-sense values without the HAL

H_HS_INTR_EDGE and H_DR_INTR_EDGE are consumed by the port's _h_config_gpio_as_interrupt implementation, which maps them onto ra8_icu_irqmd_t. They are written here as the plain integers that enumeration uses (0 falling, 1 rising, 2 both, 3 low-level) rather than as the enumerators, because including ra8_icu_regs.h would drag the HAL register map into all nineteen vendored translation units.

Symbols deliberately NOT defined here

• H_ESP_HOSTED_CLI_ENABLED and H_PEER_DATA_TRANSFER are tested with #ifdef, so defining either to zero would switch the feature ON. Both stay undefined; see the features header for the reasoning.
• H_MIN, H_FREE_PTR_WITH_FUNC, H_BUFF_ZEROCOPY, H_BUFF_NO_ZEROCOPY and H_DEFLT_FREE_FUNC are defined by the vendored transport_drv.h; H_SET_BIT / H_GET_BIT by esp_hosted_bitmasks.h; H_BIT0 .. H_BIT2 and the H_CP_GPIO_* family by esp_hosted_cp_gpio.h; H_FLOW_CTRL_* by esp_hosted_transport.h. Restating any of them with different text is a macro redefinition, which is a warning, not an improvement.
• The two per-direction SPI queue depths are likewise already defined by the vendored spi_drv.h (20 each). H_TRANSPORT_QUEUE_SIZE is kept equal to them so the transport mempool that transport_drv.c sizes from it matches the queues spi_drv.c actually creates.
• H_GPIO_MODE_DEF_*, H_GPIO_PULL_*, H_TIMER_TYPE_*, H_IRAM_ATTR and H_WEAK_REF belong to port_esp_hosted_host_os.h.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file port_esp_hosted_host_config.h.

Macro Definition Documentation

H_DATAREADY_ACTIVE_HIGH

#define H_DATAREADY_ACTIVE_HIGH   (1)

Whether the co-processor asserts DATA_READY by driving it high.

One, for the same image and the same bench observation as H_HANDSHAKE_ACTIVE_HIGH.

Note

Read-only build configuration.

Warning

An inverted harness must change this flag, not the derived level and edge macros.

Example:

#if !H_DATAREADY_ACTIVE_HIGH
invert_data_ready_tracking();
#endif

Since

0.1.0

Definition at line 538 of file port_esp_hosted_host_config.h.

H_DISABLE

#define H_DISABLE   (0)

Generic "switch this off" argument for the GPIO vtable.

Zero, the complement of H_ENABLE.

Note

Read-only build configuration.

Warning

Not a feature flag; it is a call argument.

Example:

g_h.funcs->_h_hold_gpio(reset.port, reset.pin, H_DISABLE);

Since

0.1.0

Definition at line 880 of file port_esp_hosted_host_config.h.

H_DR_INTR_EDGE

#define H_DR_INTR_EDGE   (1)

Interrupt sense the port programs for the DATA_READY input.

One, which is k_ra8_icu_irqmd_rising. This is the edge that actually wakes the transaction pump, so it is the latency-critical one.

Note

Read-only build configuration.

Warning

Integer-encoded to keep the HAL out of the vendored core; see H_HS_INTR_EDGE.

Example:

g_h.funcs->_h_config_gpio_as_interrupt(H_GPIO_DATA_READY_Port,
    H_GPIO_DATA_READY_Pin, H_DR_INTR_EDGE, gpio_dr_isr_handler, NULL);

Since

0.1.0

Definition at line 671 of file port_esp_hosted_host_config.h.

H_DR_VAL_ACTIVE

#define H_DR_VAL_ACTIVE   (1)

Level read back on DATA_READY when a frame is waiting.

One, because H_DATAREADY_ACTIVE_HIGH is 1.

Note

Read-only build configuration.

Warning

Must stay consistent with H_DR_INTR_EDGE.

Example:

uint8_t pending = (gpio_rx_data_ready == H_DR_VAL_ACTIVE);

Since

0.1.0

Definition at line 639 of file port_esp_hosted_host_config.h.

Referenced by c6_hosted_report_sideband(), and ra8_esp_hosted_port_rx_pending().

H_DR_VAL_INACTIVE

#define H_DR_VAL_INACTIVE   (0)

Level read back on DATA_READY when nothing is waiting.

Zero, the complement of H_DR_VAL_ACTIVE.

Note

Read-only build configuration.

Warning

Seeds the driver's cached level; an inconsistent pair reports a spurious first edge.

Example:

gpio_pin_state_t data_ready = H_DR_VAL_INACTIVE;

Since

0.1.0

Definition at line 654 of file port_esp_hosted_host_config.h.

H_ENABLE

#define H_ENABLE   (1)

Generic "switch this on" argument for the GPIO vtable.

One. Passed as the enable argument of _h_pull_gpio and as the hold_value of _h_hold_gpio.

Note

Read-only build configuration.

Warning

Not a feature flag; it is a call argument.

Example:

g_h.funcs->_h_pull_gpio(port, pin, H_GPIO_PULL_UP, H_ENABLE);

Since

0.1.0

Definition at line 866 of file port_esp_hosted_host_config.h.

H_ESP_HOSTED_HOST

#define H_ESP_HOSTED_HOST   (1)

Marks this build as the esp-hosted host, not the co-processor.

One. The vendored sources are shared between both ends; this is the side that drives the bus and runs the RPC client.

Note

Read-only build configuration; tested with #ifdef, so its value matters less than its presence.

Warning

Never define this in a co-processor build; the two roles compile mutually exclusive halves of the same files.

Example:

#ifdef H_ESP_HOSTED_HOST
host_side_only_command();
#endif

Since

0.1.0

Definition at line 808 of file port_esp_hosted_host_config.h.

H_ESP_PAYLOAD_HEADER_OFFSET

#define H_ESP_PAYLOAD_HEADER_OFFSET   (12)

Bytes of esp-hosted payload header in front of every frame.

Twelve, which is sizeof(struct esp_payload_header) for the layout in the vendored common/esp_hosted_header.h: a packed interface/number byte, flags, length, offset, checksum, sequence number, a throttle-and-reserved byte and the trailing one-byte union. That header defines the same macro from the sizeof; the guard means whichever header a translation unit reaches first wins, and both give 12.

Note

Read-only build configuration.

Warning

The two definitions only agree while ESP_PKT_NUM_DEBUG is off. Enabling it grows the struct to 14 and this literal becomes a lie – delete the literal rather than bump it.

Example:

memcpy(frame + H_ESP_PAYLOAD_HEADER_OFFSET, payload, len);

Since

0.1.0

Definition at line 830 of file port_esp_hosted_host_config.h.

H_GPIO_DATA_READY_Pin

#define H_GPIO_DATA_READY_Pin   RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_data_ready)

Pin index of the DATA_READY input, or -1 when it is not wired.

Derived from k_ra8_esp_hosted_pin_data_ready. The C6 asserts it while its transmit queue holds a frame for the host, and keeps it asserted until the host drains that frame.

Note

Read-only build configuration.

Warning

As wired this net (J26-8) has no ICU channel, so the port serves it with the software edge detector. That costs nothing only because the level is held: the one Pmod1 side-band net with a channel is HANDSHAKE's, which needs it, since HANDSHAKE merely pulses.

Example:

if (H_GPIO_DATA_READY_Pin != -1) { attach_data_ready_irq(); }

Since

0.1.0

Definition at line 459 of file port_esp_hosted_host_config.h.

Referenced by c6_hosted_print_pin_map(), c6_hosted_report_sideband(), esp_hosted_get_default_spi_config(), internal_configure_sideband(), and ra8_esp_hosted_port_rx_pending().

H_GPIO_DATA_READY_Port

#define H_GPIO_DATA_READY_Port   RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_data_ready)

Opaque port handle of the DATA_READY input.

Derived from k_ra8_esp_hosted_pin_data_ready; see the encoding contract in this file's header block.

Note

Read-only build configuration.

Warning

Meaningless without the matching H_GPIO_DATA_READY_Pin.

Example:

g_h.funcs->_h_read_gpio(H_GPIO_DATA_READY_Port, H_GPIO_DATA_READY_Pin);

Since

0.1.0

Definition at line 438 of file port_esp_hosted_host_config.h.

Referenced by c6_hosted_print_pin_map(), c6_hosted_report_sideband(), esp_hosted_get_default_spi_config(), internal_configure_sideband(), and ra8_esp_hosted_port_rx_pending().

H_GPIO_HANDSHAKE_Pin

#define H_GPIO_HANDSHAKE_Pin   RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_handshake)

Pin index of the HANDSHAKE input, or -1 when it is not wired.

Derived from k_ra8_esp_hosted_pin_handshake. The C6 asserts this line when it is ready for the next transaction and deasserts it on the chip-select edge.

Note

Read-only build configuration.

Warning

spi_drv.c skips interrupt teardown when this is -1; a harness without a HANDSHAKE wire runs the link on DATA_READY alone.

Example:

if (H_GPIO_HANDSHAKE_Pin != -1) { teardown_handshake_irq(); }

Since

0.1.0

Definition at line 422 of file port_esp_hosted_host_config.h.

Referenced by c6_fwver_wait_handshake(), c6_hosted_print_pin_map(), c6_hosted_report_sideband(), esp_hosted_get_default_spi_config(), internal_configure_sideband(), and internal_ra8_esp_hosted_c6link_handshake().

H_GPIO_HANDSHAKE_Port

#define H_GPIO_HANDSHAKE_Port   RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_handshake)

Opaque port handle of the HANDSHAKE input.

Derived from k_ra8_esp_hosted_pin_handshake; see the encoding contract in this file's header block.

Note

Read-only build configuration.

Warning

Meaningless without the matching H_GPIO_HANDSHAKE_Pin; the two are always passed together.

Example:

g_h.funcs->_h_read_gpio(H_GPIO_HANDSHAKE_Port, H_GPIO_HANDSHAKE_Pin);

Since

0.1.0

Definition at line 404 of file port_esp_hosted_host_config.h.

Referenced by c6_fwver_wait_handshake(), c6_hosted_print_pin_map(), c6_hosted_report_sideband(), esp_hosted_get_default_spi_config(), internal_configure_sideband(), and internal_ra8_esp_hosted_c6link_handshake().

H_GPIO_PIN_RESET

#define H_GPIO_PIN_RESET   RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_reset)

Pin index of the co-processor reset output, or -1 when unwired.

Minus one on this harness: coprocessor/esp32c6/pins.env records the C6 reset input as disconnected, so the pin table sets k_ra8_esp_hosted_pin_reset to k_ra8_pin_none.

Note

Read-only build configuration.

Warning

With no reset wire the host cannot recover a wedged co-processor; it has to be power-cycled. Wiring one is a pin-table edit only.

Example:

if (H_GPIO_PIN_RESET != -1) { pulse_coprocessor_reset(); }

Since

0.1.0

Definition at line 492 of file port_esp_hosted_host_config.h.

Referenced by c6_hosted_print_pin_map(), and esp_hosted_get_default_spi_config().

H_GPIO_PORT_RESET

#define H_GPIO_PORT_RESET   RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_reset)

Opaque port handle of the co-processor reset output.

Derived from k_ra8_esp_hosted_pin_reset. Used as the fall-back reset pin before any transport configuration has been set.

Note

Read-only build configuration.

Warning

Upstream spells this one _PORT_ in the middle, unlike the CamelCase side-band pair above; both spellings are mandatory.

Example:

gpio_pin_t reset = { .port = H_GPIO_PORT_RESET, .pin = H_GPIO_PIN_RESET };

Since

0.1.0

Definition at line 475 of file port_esp_hosted_host_config.h.

Referenced by c6_hosted_print_pin_map(), and esp_hosted_get_default_spi_config().

H_HANDSHAKE_ACTIVE_HIGH

#define H_HANDSHAKE_ACTIVE_HIGH   (1)

Whether the co-processor asserts HANDSHAKE by driving it high.

One. The stock esp-hosted C6 image drives HANDSHAKE high to say "ready for the next transaction"; the bench probe saw the same.

Note

Read-only build configuration.

Warning

spi_drv.c inverts its own bookkeeping when this is 0; do not also invert the derived values by hand.

Example:

#if !H_HANDSHAKE_ACTIVE_HIGH
invert_handshake_tracking();
#endif

Since

0.1.0

Definition at line 520 of file port_esp_hosted_host_config.h.

H_HS_INTR_EDGE

#define H_HS_INTR_EDGE   (1)

Interrupt sense the port programs for the HANDSHAKE input.

One, which is k_ra8_icu_irqmd_rising – the asserting edge of an active-high line. Written as an integer so the HAL register header does not have to be visible to the vendored core.

Note

Read-only build configuration.

Warning

If the ICU sense encoding ever changes, this integer and ra8_icu_irqmd_t drift apart silently; the port's own conversion is where that is asserted.

Example:

g_h.funcs->_h_config_gpio_as_interrupt(H_GPIO_HANDSHAKE_Port,
    H_GPIO_HANDSHAKE_Pin, H_HS_INTR_EDGE, gpio_hs_isr_handler, NULL);

Since

0.1.0

Definition at line 589 of file port_esp_hosted_host_config.h.

H_HS_VAL_ACTIVE

#define H_HS_VAL_ACTIVE   (1)

Level read back on HANDSHAKE when it is asserted.

One, because H_HANDSHAKE_ACTIVE_HIGH is 1.

Note

Read-only build configuration.

Warning

Must stay consistent with H_HS_INTR_EDGE or the driver waits for an edge that never arrives on the level it then tests.

Example:

if (gpio_handshake == H_HS_VAL_ACTIVE) { start_transaction(); }

Since

0.1.0

Definition at line 555 of file port_esp_hosted_host_config.h.

Referenced by c6_fwver_wait_handshake(), c6_hosted_report_sideband(), and internal_ra8_esp_hosted_c6link_handshake().

H_HS_VAL_INACTIVE

#define H_HS_VAL_INACTIVE   (0)

Level read back on HANDSHAKE when it is deasserted.

Zero, the complement of H_HS_VAL_ACTIVE.

Note

Read-only build configuration.

Warning

The SPI driver seeds its cached level with this before the first read, so an inconsistent pair reports a spurious first edge.

Example:

gpio_pin_state_t handshake = H_HS_VAL_INACTIVE;

Since

0.1.0

Definition at line 570 of file port_esp_hosted_host_config.h.

H_RESET_VAL_ACTIVE

#define H_RESET_VAL_ACTIVE   (0)

Level that holds the co-processor in reset.

Zero: the ESP32 reset input (EN) is active-low, so asserting reset means driving the line low.

Note

Read-only build configuration.

Warning

Only reached when a reset pin is wired; see H_GPIO_PIN_RESET.

Example:

g_h.funcs->_h_write_gpio(reset.port, reset.pin, H_RESET_VAL_ACTIVE);

Since

0.1.0

Definition at line 724 of file port_esp_hosted_host_config.h.

H_RESET_VAL_INACTIVE

#define H_RESET_VAL_INACTIVE   (1)

Level that releases the co-processor from reset.

One, the complement of H_RESET_VAL_ACTIVE.

Note

Read-only build configuration.

Warning

The line must be released before the boot event can arrive; the transport waits for that event and gives up without it.

Example:

g_h.funcs->_h_write_gpio(reset.port, reset.pin, H_RESET_VAL_INACTIVE);

Since

0.1.0

Definition at line 739 of file port_esp_hosted_host_config.h.

Referenced by internal_config_gpio().

H_SLAVE_TARGET_ESP32

#define H_SLAVE_TARGET_ESP32   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an original ESP32.

Zero. Also read by sdio_reg.h to pick a register layout, which is another reason it must be honest rather than merely unused.

Note

Read-only build configuration.

Warning

Setting this alongside the C6 selector makes the host expect the wrong chip id and refuse the link.

Example:

#if H_SLAVE_TARGET_ESP32 // LEGACY-OK: upstream esp-hosted macro name
exp_chip_id = ESP_PRIV_FIRMWARE_CHIP_ESP32;
#endif

Since

0.1.0

Definition at line 254 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32C2

#define H_SLAVE_TARGET_ESP32C2   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-C2.

Zero; no C2 module exists on this bench.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 263 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32C3

#define H_SLAVE_TARGET_ESP32C3   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-C3.

Zero; no C3 module exists on this bench.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 272 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32C5

#define H_SLAVE_TARGET_ESP32C5   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-C5.

Zero. Also consulted by sdio_reg.h.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 281 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32C6

#define H_SLAVE_TARGET_ESP32C6   (1) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor on this board is an ESP32-C6.

One. coprocessor/esp32c6/pins.env pins the module, the ESP-IDF version (v5.5.4) and the esp-hosted-mcu commit it is built from; the part reports chip id 0x0D in its boot event.

Note

Read-only build configuration.

Warning

Exactly one target macro may be 1. The vendored selection is an #if / #elif chain, so a second 1 is silently ignored and the wrong chip id is expected.

Example:

#if H_SLAVE_TARGET_ESP32C6 // LEGACY-OK: upstream esp-hosted macro name
exp_chip_id = ESP_PRIV_FIRMWARE_CHIP_ESP32C6;
#endif

Since

0.1.0

Definition at line 237 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32C61

#define H_SLAVE_TARGET_ESP32C61   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-C61.

Zero. Also consulted by sdio_reg.h.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 290 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32H2

#define H_SLAVE_TARGET_ESP32H2   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-H2.

Zero; the H2 has no Wi-Fi radio, which is the point of this link.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 299 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32H4

#define H_SLAVE_TARGET_ESP32H4   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-H4.

Zero; no H4 module exists on this bench.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 308 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32S2

#define H_SLAVE_TARGET_ESP32S2   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-S2.

Zero; no S2 module exists on this bench.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 317 of file port_esp_hosted_host_config.h.

H_SLAVE_TARGET_ESP32S3

#define H_SLAVE_TARGET_ESP32S3   (0) /* LEGACY-OK: upstream esp-hosted macro name */

The co-processor is not an ESP32-S3.

Zero; no S3 module exists on this bench.

Note

Read-only build configuration.

Warning

Exactly one target selector may be 1; see the C6 one above.

Since

0.1.0

Definition at line 326 of file port_esp_hosted_host_config.h.

H_SPI_FD_CLK_MHZ

#define H_SPI_FD_CLK_MHZ   (5)

Full-duplex SPI clock, in megahertz.

Five: a deliberately conservative first-light rate. The landed link probe clocked at 1 MHz, the C6 full-duplex peripheral tolerates up to 40, and the RA8 side runs on the SCI Simple-SPI backend, which is a polled byte engine – the ceiling here is host software, not the wire. Five is fast enough that a 1600-byte frame is not the bottleneck and slow enough that a marginal Pmod harness still latches.

Note

Read-only build configuration.

Warning

spi_drv.c logs a hint whenever this is under 40; that hint is about the co-processor's limit, not this board's.

Example:

spi_config.clk_mhz = H_SPI_FD_CLK_MHZ;

Since

0.1.0

Definition at line 851 of file port_esp_hosted_host_config.h.

Referenced by esp_hosted_get_default_spi_config().

H_TRANSPORT_IN_USE

#define H_TRANSPORT_IN_USE   (H_TRANSPORT_SPI)

The transport this image actually drives.

H_TRANSPORT_SPI. Both ends must agree: the co-processor image sets CONFIG_ESP_SPI_HOST_INTERFACE=y and CONFIG_SPI_HSPI=y in coprocessor/esp32c6/sdkconfig.defaults.

Note

Read-only build configuration.

Warning

Changing this without rebuilding and reflashing the C6 leaves the host clocking a bus the co-processor is not listening on.

Example:

#if H_TRANSPORT_IN_USE == H_TRANSPORT_SPI
transport = spi_get_handle();
#endif

Since

0.1.0

Definition at line 207 of file port_esp_hosted_host_config.h.

H_TRANSPORT_NONE

#define H_TRANSPORT_NONE   (0)

No transport has been configured yet.

Zero, and the initial value of the transport-configuration union's discriminant. esp_hosted_transport_get_reset_config() treats it as "fall back to the compile-time reset pin".

Note

Read-only build configuration.

Warning

Never assign this to H_TRANSPORT_IN_USE; the vendored default config function returns an error when no transport is selected.

Example:

case H_TRANSPORT_NONE: use_compile_time_reset_pin(); break;

Since

0.1.0

Definition at line 114 of file port_esp_hosted_host_config.h.

H_TRANSPORT_QUEUE_SIZE

#define H_TRANSPORT_QUEUE_SIZE   (20)

Frames a single transport direction can hold.

Twenty, matching the per-direction depths the vendored spi_drv.h already hard-codes. transport_drv.c sizes the shared mempool from this value, so keeping the two equal is what stops the pool running dry while the queues still have room.

Note

Read-only build configuration.

Warning

Twenty 1600-byte frames per direction is roughly 64 KiB of pool; raising it costs SRAM the display and storage layers also want.

Example:

config.num_blocks = H_TRANSPORT_QUEUE_SIZE + MEMPOOL_PADDING;

Since

0.1.0

Definition at line 761 of file port_esp_hosted_host_config.h.

H_TRANSPORT_SDIO

#define H_TRANSPORT_SDIO   (2)

Transport id of the SDIO link.

Two. Not used on this board: the only SDHI socket carries the SD card, and the C6 module is wired to a Pmod SPI position.

Note

Read-only build configuration.

Warning

sdio_drv.c still compiles; its constants live in port_esp_hosted_host_config_transports.h.

Example:

#if H_TRANSPORT_IN_USE == H_TRANSPORT_SDIO
sdio_bus_init();
#endif

Since

0.1.0

Definition at line 152 of file port_esp_hosted_host_config.h.

H_TRANSPORT_SPI

#define H_TRANSPORT_SPI   (1)

Transport id of the full-duplex SPI link.

One. This is the transport the EK-RA8D2 uses: four wires plus HANDSHAKE and DATA_READY, matching the ESP32-C6 image built from coprocessor/esp32c6/.

Note

Read-only build configuration.

Warning

Selecting it makes transport_drv.h include port_esp_hosted_host_spi.h, which is where the frame size lives.

Example:

#if H_TRANSPORT_IN_USE == H_TRANSPORT_SPI
#include "port_esp_hosted_host_spi.h"
#endif

Since

0.1.0

Definition at line 134 of file port_esp_hosted_host_config.h.

H_TRANSPORT_SPI_HD

#define H_TRANSPORT_SPI_HD   (3)

Transport id of the half-duplex (1/2/4-line) SPI link.

Three. Not used: the C6 image is built with CONFIG_ESP_SPI_HOST_INTERFACE, the full-duplex mode.

Note

Read-only build configuration.

Warning

Half-duplex needs a DATA_READY line the full-duplex driver also claims; the two transports cannot coexist on one harness.

Example:

#if H_TRANSPORT_IN_USE == H_TRANSPORT_SPI_HD
spi_hd_set_data_lines(H_SPI_HD_CONFIG_4_DATA_LINES);
#endif

Since

0.1.0

Definition at line 170 of file port_esp_hosted_host_config.h.

H_TRANSPORT_UART

#define H_TRANSPORT_UART   (4)

Transport id of the UART link.

Four. Not used: a byte-framed UART cannot carry the 1600-byte frames the rest of this port is sized for at any useful rate.

Note

Read-only build configuration.

Warning

uart_drv.c still compiles; its constants live in port_esp_hosted_host_config_transports.h.

Example:

#if H_TRANSPORT_IN_USE == H_TRANSPORT_UART
uart_open_link();
#endif

Since

0.1.0

Definition at line 188 of file port_esp_hosted_host_config.h.

RA8_ESP_HOSTED_GPIO_PIN

#define RA8_ESP_HOSTED_GPIO_PIN

(

pin_code

)

Value:

(((uint16_t)(pin_code) == (uint16_t)k_ra8_pin_none) ? (-1) : (int)RA8_PIN_PIN(pin_code))

Extract the int pin half of a packed RA8 pin, or -1 if unwired.

Decodes the low byte with RA8_PIN_PIN(), except that the k_ra8_pin_none sentinel maps to -1 – the value the vendored SPI driver tests against before it configures or tears down a side-band interrupt.

Both sides of the sentinel test are narrowed to uint16_t first. The argument and k_ra8_pin_none come from different enumerations, and comparing two enumerated types directly is a -Wenum-compare error under this project's warning settings.

Parameters

[in]

pin_code

Packed RA8_PIN(port, pin) value, or k_ra8_pin_none.

Note

Read-only build configuration; expands to a constant expression.

Warning

The vtable takes uint32_t for the pin, so a -1 that reaches a call converts to 0xFFFFFFFF. Guard the call, as spi_drv.c does.

Example:

if (RA8_ESP_HOSTED_GPIO_PIN(k_ra8_esp_hosted_pin_reset) != -1) { hold(); }

Since

0.1.0

Definition at line 376 of file port_esp_hosted_host_config.h.

Referenced by esp_hosted_get_default_spi_config().

RA8_ESP_HOSTED_GPIO_PORT

#define RA8_ESP_HOSTED_GPIO_PORT

(

pin_code

)

Value:

((void*)(uintptr_t)RA8_PIN_PORT(pin_code))

Extract the void* port half of a packed RA8 pin.

Decodes the high byte of a ra8_port_pin_t with RA8_PIN_PORT() and carries it through uintptr_t into the opaque pointer the vendored vtable takes. Port 0 therefore yields a null pointer, which is a valid encoding here: the port decodes the integer back and range-checks it, and never treats null as "absent".

Parameters

[in]

pin_code

Packed RA8_PIN(port, pin) value.

Note

Read-only build configuration; expands to a constant expression.

Warning

Do not dereference the result. It is an index in pointer clothing, not an address.

Example:

void *port = RA8_ESP_HOSTED_GPIO_PORT(k_ra8_esp_hosted_pin_handshake);

Since

0.1.0

Definition at line 350 of file port_esp_hosted_host_config.h.

Referenced by esp_hosted_get_default_spi_config().