port_esp_hosted_host_config_transports.h

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#pragma once
 
/* ----------------------------------------------------------------------- */
/* Half-duplex SPI */
/* ----------------------------------------------------------------------- */

#define H_SPI_HD_HOST_INTERFACE (0)

#define H_SPI_HD_HOST_NUM_DATA_LINES (4)

#define H_SPI_HD_CONFIG_1_DATA_LINE (1)

#define H_SPI_HD_CONFIG_2_DATA_LINES (2)

#define H_SPI_HD_CONFIG_4_DATA_LINES (4)

#define H_SPI_HD_CLK_MHZ (5)

#define H_SPI_HD_CHECKSUM (1)

#define H_SPI_HD_DATA_READY_ENABLED (1)

#define H_SPI_HD_PORT_DATA_READY (H_GPIO_DATA_READY_Port)

#define H_SPI_HD_PIN_DATA_READY (H_GPIO_DATA_READY_Pin)

#define H_SPI_HD_DR_INTR_EDGE (H_DR_INTR_EDGE)

#define H_SPI_HD_POLL_INTERVAL_MS (10)

#define H_SPI_HD_TX_QUEUE_SIZE (H_TRANSPORT_QUEUE_SIZE)

#define H_SPI_HD_RX_QUEUE_SIZE (H_TRANSPORT_QUEUE_SIZE)
 
/* ----------------------------------------------------------------------- */
/* SDIO */
/* ----------------------------------------------------------------------- */

#define H_SDIO_ALWAYS_HOST_RX_MAX_TRANSPORT_SIZE (1)

#define H_SDIO_HOST_STREAMING_MODE (2)

#define H_SDIO_HOST_RX_MODE (0)

#define H_SDIO_CHECKSUM (1)

#define H_SDIO_CLOCK_FREQ_KHZ (40000)

#define H_SDIO_TX_BLOCK_ONLY_XFER (0)

#define H_SDIO_RX_BLOCK_ONLY_XFER (0)

#define H_HOST_SDIO_RESET_DELAY_MS (100)

#define H_SLAVE_RESET_ONLY_IF_NECESSARY (0) /* LEGACY-OK: upstream esp-hosted macro name */

#define H_RESET_ON_EVERY_BOOTUP (1)

#define H_TRANSPORT_RESTART_ON_FAILURE (0)
 
/* ----------------------------------------------------------------------- */
/* UART */
/* ----------------------------------------------------------------------- */

#define H_UART_HOST_TRANSPORT (0)

#define H_UART_CHECKSUM (1)

#define H_UART_TX_QUEUE_SIZE (H_TRANSPORT_QUEUE_SIZE)

#define H_UART_RX_QUEUE_SIZE (H_TRANSPORT_QUEUE_SIZE)