ra8_esp_hosted_spi.c

Go to the documentation of this file.

 
#include <stdint.h>
 
/*
 * ``port_esp_hosted_host_config.h`` is deliberately NOT named here even
 * though this file depends on it. It defines H_ESP_PAYLOAD_HEADER_OFFSET
 * under an #ifndef guard, while the vendored ``esp_hosted_header.h`` defines
 * the same macro unconditionally from a sizeof; whichever is reached first
 * wins and the other is skipped. ``transport_drv.h`` pulls them in that
 * order. Naming the config header here would sort it ahead of
 * ``transport_drv.h`` and turn the arrangement into a redefinition warning.
 */
#include "port_esp_hosted_host_os.h"
#include "port_esp_hosted_host_spi.h"
#include "ra8_attributes.h"
#include "ra8_board_ek_ra8d2_connectors.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_esp_hosted_pins.h"
#include "ra8_esp_hosted_spi_internal.h"
#include "ra8_gpio_constants.h"
#include "ra8_io_spi_bus.h"
#include "ra8_io_spi_bus_sci_spi.h"
#include "ra8_log.h"
#include "ra8_pin_interface.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_sci_spi.h"
#include "ra8_spi.h"
#include "transport_drv.h"

static const char* const s_tag = "eh_spi";

typedef enum : uint16_t {
  k_ra8_esp_hosted_spi_frame_bytes = (uint16_t)MAX_TRANSPORT_BUFFER_SIZE,
} ra8_esp_hosted_spi_frame_t;
 
static_assert((uint8_t)k_ra8_esp_hosted_spi_mode == (uint8_t)k_ra8_spi_mode_3,
              "the co-processor image is built CONFIG_ESP_SPI_MODE=3");
/*
 * Not a tautology: the left operand is the bound reached through
 * ``MAX_TRANSPORT_BUFFER_SIZE``, which ``transport_drv.h`` resolves through
 * whichever port header its ``H_TRANSPORT_IN_USE`` chain selected, while the
 * right is the constant the vendored ``spi_drv.c`` clocks. Selecting a
 * different transport, or editing this port's SPI header to a hand-written
 * number, makes them disagree and stops the build here rather than on the
 * wire.
 */
static_assert(k_ra8_esp_hosted_spi_frame_bytes == MAX_SPI_BUFFER_SIZE,
              "the port's frame bound must be the one the vendored SPI driver clocks");

static ra8_io_spi_bus_t s_bus;

static const ra8_io_spi_bus_t* s_injected_bus;

static const ra8_pin_interface_t* s_pin_if;

static uint8_t s_channel;

static bool s_open;
 
/*
 * The production pin driver is defined in libs/ra8_hal/src/gpio.c and, like
 * every other consumer of it in this tree, is reached by declaration rather
 * than through a header -- ra8_pin_interface.h describes the type, not the
 * instance.
 */
extern const ra8_pin_interface_t g_ra8_gpio_pin_interface;

RA8_INTERNAL
static const ra8_pin_interface_t* internal_pin_if(void)
{
  return (s_pin_if != nullptr) ? s_pin_if : &g_ra8_gpio_pin_interface;
}

RA8_INTERNAL
static const ra8_io_spi_bus_t* internal_bus(void)
{
  if (s_injected_bus != nullptr) {
    return s_injected_bus;
  }
  return (s_bus.iface != nullptr) ? &s_bus : nullptr;
}

RA8_INTERNAL
static ra8_err_t internal_route_data_pins(void)
{
  ra8_err_t err = ra8_pfs_route_peripheral((ra8_port_pin_t)k_ra8_board_pmod1_spi_sck,
                                           k_ra8_psel_sci_async,
                                           "esp_hosted.sck");
  if (err != k_ra8_ok) {
    return err;
  }
  err = ra8_pfs_route_peripheral((ra8_port_pin_t)k_ra8_board_pmod1_spi_copi,
                                 k_ra8_psel_sci_async,
                                 "esp_hosted.copi");
  if (err != k_ra8_ok) {
    return err;
  }
  return ra8_pfs_route_peripheral((ra8_port_pin_t)k_ra8_board_pmod1_spi_cipo,
                                  k_ra8_psel_sci_async,
                                  "esp_hosted.cipo");
}

RA8_INTERNAL
static void internal_release_pins(void)
{
  (void)ra8_gpio_release((ra8_port_pin_t)k_ra8_board_pmod1_spi_sck);
  (void)ra8_gpio_release((ra8_port_pin_t)k_ra8_board_pmod1_spi_copi);
  (void)ra8_gpio_release((ra8_port_pin_t)k_ra8_board_pmod1_spi_cipo);
  (void)ra8_gpio_release((ra8_port_pin_t)k_ra8_esp_hosted_pin_chip_select);
}
 
RA8_PRIV ra8_err_t priv_ra8_esp_hosted_spi_open(uint8_t  sci_channel,
                                                uint32_t pclk_hz,
                                                uint32_t sck_hz)
{
  if (s_open) {
    return k_ra8_err_invalid_state;
  }
  if ((pclk_hz == 0U) || (sck_hz == 0U) ||
      (sci_channel != (uint8_t)k_ra8_board_pmod1_sci_channel)) {
    return k_ra8_err_invalid_arg;
  }
 
  ra8_err_t err = internal_route_data_pins();
  if (err == k_ra8_ok) {
    const ra8_pin_interface_t* pin_if = internal_pin_if();
    err = pin_if->output_init(pin_if->ctx,
                              (ra8_port_pin_t)k_ra8_esp_hosted_pin_chip_select,
                              k_ra8_level_high);
  }
  if (err != k_ra8_ok) {
    internal_release_pins();
    ra8_log_error_val(s_tag, "pin setup failed", (uint32_t)err);
    return err;
  }
 
  const ra8_sci_spi_cfg_t cfg = {
    .baud_hz   = sck_hz,
    .pclk_hz   = pclk_hz,
    .mode      = (ra8_spi_mode_t)k_ra8_esp_hosted_spi_mode,
    .lsb_first = false,
  };
  err = ra8_sci_spi_init(sci_channel, &cfg);
  if (err == k_ra8_ok) {
    err = ra8_io_spi_bus_bind_sci_spi(&s_bus, sci_channel);
  }
  if (err != k_ra8_ok) {
    (void)ra8_sci_spi_deinit(sci_channel);
    internal_release_pins();
    s_bus = (ra8_io_spi_bus_t){};
    ra8_log_error_val(s_tag, "sci simple-spi open failed", (uint32_t)err);
    return k_ra8_err_spi_error;
  }
 
  s_channel = sci_channel;
  s_open    = true;
  ra8_log_info_val(s_tag, "bus open on sci channel", (uint32_t)sci_channel);
  return k_ra8_ok;
}
 
RA8_PRIV ra8_err_t priv_ra8_esp_hosted_spi_close(void)
{
  if (!s_open) {
    return k_ra8_err_not_initialized;
  }
  const ra8_err_t err = ra8_sci_spi_deinit(s_channel);
  internal_release_pins();
  s_bus  = (ra8_io_spi_bus_t){};
  s_open = false;
  return (err == k_ra8_ok) ? k_ra8_ok : k_ra8_err_spi_error;
}
 
RA8_PRIV bool priv_ra8_esp_hosted_spi_is_open(void)
{
  return s_open;
}
 
RA8_PRIV void priv_ra8_esp_hosted_spi_set_bus(const ra8_io_spi_bus_t* bus)
{
  s_injected_bus = bus;
}
 
RA8_PRIV void priv_ra8_esp_hosted_spi_set_pin_interface(const ra8_pin_interface_t* iface)
{
  s_pin_if = iface;
}

RA8_INTERNAL
static void* internal_bus_init(void)
{
  if (internal_bus() == nullptr) {
    ra8_log_warn(s_tag, "bus init before the port opened the channel");
    return nullptr;
  }
  return &s_bus;
}

RA8_INTERNAL
static int internal_bus_deinit(void* bus_handle)
{
  if (bus_handle == nullptr) {
    return RET_INVALID;
  }
  if (bus_handle != (void*)&s_bus) {
    return RET_INVALID;
  }
  return (priv_ra8_esp_hosted_spi_close() == k_ra8_ok) ? RET_OK : RET_FAIL;
}

RA8_INTERNAL
static int internal_do_bus_transfer(void* transfer_context)
{
  struct hosted_transport_context_t* ctx = (struct hosted_transport_context_t*)transfer_context;
  if (ctx == nullptr) {
    return RET_INVALID;
  }
  if ((ctx->tx_buf == nullptr) || (ctx->rx_buf == nullptr)) {
    return RET_INVALID;
  }
  if ((ctx->tx_buf_size == 0U) || (ctx->tx_buf_size > (uint32_t)MAX_TRANSPORT_BUFFER_SIZE)) {
    return RET_INVALID;
  }
  const ra8_io_spi_bus_t* bus = internal_bus();
  if (bus == nullptr) {
    return RET_FAIL;
  }
 
  const ra8_pin_interface_t* pin_if = internal_pin_if();
  const ra8_port_pin_t       cs     = (ra8_port_pin_t)k_ra8_esp_hosted_pin_chip_select;
  if (pin_if->write(pin_if->ctx, cs, k_ra8_level_low) != k_ra8_ok) {
    return RET_FAIL;
  }
  const ra8_err_t err =
    ra8_io_spi_bus_write_read(bus, ctx->tx_buf, ctx->rx_buf, ctx->tx_buf_size, k_ra8_spi_width_8);
  const ra8_err_t cs_err = pin_if->write(pin_if->ctx, cs, k_ra8_level_high);
  if (err != k_ra8_ok) {
    ra8_log_error_val(s_tag, "frame transfer failed", (uint32_t)err);
    return RET_FAIL;
  }
  return (cs_err == k_ra8_ok) ? RET_OK : RET_FAIL;
}
 
RA8_PRIV ra8_err_t priv_ra8_esp_hosted_spi_bind(hosted_osi_funcs_t* out)
{
  RA8_CHECK_NULL_PTR(out, s_tag, "vtable must not be nullptr");
  out->_h_bus_init        = internal_bus_init;
  out->_h_bus_deinit      = internal_bus_deinit;
  out->_h_do_bus_transfer = internal_do_bus_transfer;
  return (out->_h_do_bus_transfer != nullptr) ? k_ra8_ok : k_ra8_err_invalid_state;
}