ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_pcntr.h
Go to the documentation of this file.
1
53
54#pragma once
55
56#ifdef __cplusplus
57extern "C" {
58#endif
59
60#include <stdint.h>
61
62#include "ra8_err.h"
63#include "ra8_port_constants.h"
64#include "ra8_port_regs.h"
65
98[[nodiscard]] static inline ra8_err_t
100{
101 if ((uint8_t)port > (uint8_t)k_ra8_port_max) {
103 }
104 if ((uint8_t)pin > (uint8_t)k_ra8_pin_max) {
106 }
107
108 volatile r_port_regs_t* port_regs = ra8_port(port);
109 if (port_regs == nullptr) {
111 }
112
113 const uint32_t pdr_mask = (uint32_t)(1UL << (uint32_t)pin);
114 const uint32_t podr_mask = pdr_mask << (uint32_t)k_ra8_pcntr_high_half_shift;
115
116 /* HUM Ch 20.2 "PCNTR1/PODR/PDR : Port Control Register 1" p 840 -- read {PODR, PDR}
117 * so the sibling pins on this port are preserved across the update. */
118 uint32_t pcntr1 = port_regs->PCNTR1;
119 pcntr1 |= pdr_mask; /* PDR[pin] = 1 -> this pin is an output. */
120 if (level == k_ra8_level_high) {
121 pcntr1 |= podr_mask; /* PODR[pin] = 1 -> drive high. */
122 } else {
123 pcntr1 &= ~podr_mask; /* PODR[pin] = 0 -> drive low. */
124 }
125 /* HUM Ch 20.2 "PCNTR1/PODR/PDR : Port Control Register 1" p 840 -- write {PODR, PDR}:
126 * commit the pin as an output at the requested level. */
127 port_regs->PCNTR1 = pcntr1;
128 return k_ra8_ok;
129}
130
161[[nodiscard]] static inline ra8_err_t
163{
164 if (out_level == nullptr) {
165 return k_ra8_err_null_ptr;
166 }
167 if ((uint8_t)port > (uint8_t)k_ra8_port_max) {
169 }
170 if ((uint8_t)pin > (uint8_t)k_ra8_pin_max) {
172 }
173
174 volatile r_port_regs_t* port_regs = ra8_port(port);
175 if (port_regs == nullptr) {
177 }
178
179 /* HUM Ch 20.2 "PCNTR2/EIDR/PIDR : Port Control Register 2" p 841 -- read PIDR: the live
180 * pin state in the low half of the register. */
181 const uint32_t pidr = port_regs->PCNTR2;
182 const uint32_t pin_mask = (uint32_t)(1UL << (uint32_t)pin);
183 *out_level = ((pidr & pin_mask) != 0U) ? k_ra8_level_high : k_ra8_level_low;
184 return k_ra8_ok;
185}
186
187#ifdef __cplusplus
188}
189#endif
ra8_board_eth_pin_t pin
Pin.
Error Code Definitions for ra8-firmware.
@ k_ra8_err_hw_unmapped
Peripheral register block is not mapped in this MCU variant.
Definition ra8_err.h:345
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
Definition ra8_err.h:119
@ k_ra8_err_null_ptr
Pointer was NULL where a valid pointer was required.
Definition ra8_err.h:478
@ k_ra8_err_gpio_invalid_pin
GPIO pin index out of range within its port (valid: 0..15).
Definition ra8_err.h:331
@ k_ra8_err_gpio_invalid_port
GPIO port index out of range for this MCU.
Definition ra8_err.h:325
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Definition ra8_err.h:546
static ra8_err_t ra8_pcntr_read(ra8_port_t port, ra8_pin_t pin, ra8_level_t *out_level)
Read a pin's live level from PCNTR2 (PIDR).
Definition ra8_pcntr.h:162
static ra8_err_t ra8_pcntr_set_output(ra8_port_t port, ra8_pin_t pin, ra8_level_t level)
Hold a pin an output and drive it to a level, via PCNTR1 (combined).
Definition ra8_pcntr.h:99
Typed Port / Pin Constants for the RA8D2 IOPORT Module.
ra8_port_t
Port indices for the RA8D2 IOPORT module.
@ k_ra8_port_max
Highest valid port index.
ra8_level_t
Digital output / input level.
@ k_ra8_level_high
Drive or read 1.
@ k_ra8_level_low
Drive or read 0.
ra8_pin_t
Pin indices within an IOPORT port (0..15).
@ k_ra8_pin_max
Highest valid pin index.
IOPORT (GPIO) register layout for the Renesas RA8D2.
@ k_ra8_pcntr_high_half_shift
PODR/EIDR/PORR/EORR half.
static volatile r_port_regs_t * ra8_port(ra8_port_t port)
Get the PORT register window for a given port index.
Per-port IOPORT register window.
volatile uint32_t PCNTR2
PCNTR2 – { EIDR[31:16], PIDR[15:0] } (read-only).
volatile uint32_t PCNTR1
PCNTR1 – { PODR[31:16], PDR[15:0] }.