|
ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
|
Per-port IOPORT register window. More...
#include <ra8_port_regs.h>
Data Fields | |
| volatile uint32_t | PCNTR1 |
| PCNTR1 – { PODR[31:16], PDR[15:0] }. | |
| volatile uint32_t | PCNTR2 |
| PCNTR2 – { EIDR[31:16], PIDR[15:0] } (read-only). | |
| volatile uint32_t | PCNTR3 |
| PCNTR3 – { PORR[31:16], POSR[15:0] } (write-only). | |
| volatile uint32_t | PCNTR4 |
| PCNTR4 – { EORR[31:16], EOSR[15:0] }. | |
Per-port IOPORT register window.
Four 32-bit registers back-to-back. The full 32-byte port slot leaves 16 bytes of reserved space after PCNTR4; we only model the used prefix.
Definition at line 100 of file ra8_port_regs.h.
| volatile uint32_t r_port_regs_t::PCNTR1 |
PCNTR1 – { PODR[31:16], PDR[15:0] }.
Write the low half to configure direction (0 = input, 1 = output), write the high half to drive the output latch.
Definition at line 107 of file ra8_port_regs.h.
Referenced by ra8_gpio_toggle(), and ra8_pcntr_set_output().
| volatile uint32_t r_port_regs_t::PCNTR2 |
PCNTR2 – { EIDR[31:16], PIDR[15:0] } (read-only).
Low half reads live pin state. High half is event-input data, used when the port is routed through the ELC event matrix.
Definition at line 114 of file ra8_port_regs.h.
Referenced by cam_read_probe_data(), cam_read_probe_sync(), internal_ra8_epaper_wait_ready(), ra8_gpio_read(), and ra8_pcntr_read().
| volatile uint32_t r_port_regs_t::PCNTR3 |
PCNTR3 – { PORR[31:16], POSR[15:0] } (write-only).
Atomic set / atomic clear. Writing a 1 bit to POSR drives the pin high; writing a 1 bit to PORR drives it low; zero bits are ignored. This is race-free and should be used in preference to PODR RMW.
Definition at line 123 of file ra8_port_regs.h.
Referenced by ra8_gpio_toggle(), and ra8_gpio_write().
| volatile uint32_t r_port_regs_t::PCNTR4 |
PCNTR4 – { EORR[31:16], EOSR[15:0] }.
Event-driven output set / reset. Used with the ELC.
Definition at line 129 of file ra8_port_regs.h.