ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_port_regs.h
Go to the documentation of this file.
1
46
47#pragma once
48
49#ifdef __cplusplus
50extern "C" {
51#endif
52
53#include <stddef.h>
54#include <stdint.h>
55
56#include "ra8_attributes.h"
57#include "ra8_bit_constants.h"
58#include "ra8_port_constants.h"
59
60/* =============================================================================
61 * Base addresses
62 * =============================================================================
63 */
64
65typedef enum : uintptr_t {
66 k_ra8_port0_base_addr = 0x40400000UL,
67 k_ra8_port1_base_addr = 0x40400020UL,
68 k_ra8_port2_base_addr = 0x40400040UL,
69 k_ra8_port3_base_addr = 0x40400060UL,
70 k_ra8_port4_base_addr = 0x40400080UL,
71 k_ra8_port5_base_addr = 0x404000A0UL,
72 k_ra8_port6_base_addr = 0x404000C0UL,
73 k_ra8_port7_base_addr = 0x404000E0UL,
74 k_ra8_port8_base_addr = 0x40400100UL,
75 k_ra8_port9_base_addr = 0x40400120UL,
76 k_ra8_port10_base_addr = 0x40400140UL,
77 k_ra8_port11_base_addr = 0x40400160UL,
78 k_ra8_port12_base_addr = 0x40400180UL,
79 k_ra8_port13_base_addr = 0x404001A0UL,
80 k_ra8_port14_base_addr = 0x404001C0UL,
83
84/* =============================================================================
85 * Register layout (16 bytes per port)
86 * =============================================================================
87 */
88
100typedef struct {
107 volatile uint32_t PCNTR1;
114 volatile uint32_t PCNTR2;
123 volatile uint32_t PCNTR3;
129 volatile uint32_t PCNTR4;
131
133typedef enum : uint8_t {
136
137static_assert(sizeof(r_port_regs_t) == (size_t)k_ra8_port_regs_bytes,
138 "r_port_regs_t must be exactly 16 bytes");
139
140/* =============================================================================
141 * Per-port accessor functions
142 * =============================================================================
143 */
144
157static inline volatile r_port_regs_t* ra8_port(ra8_port_t port)
158{
159 if ((uint8_t)port > k_ra8_port_max) {
160 return nullptr;
161 }
162 const uintptr_t addr = k_ra8_port0_base_addr + ((uintptr_t)port * k_ra8_port_stride);
163 return (volatile r_port_regs_t*)addr;
164}
165
168static inline volatile r_port_regs_t* ra8_port0(void)
169{
170 return (volatile r_port_regs_t*)k_ra8_port0_base_addr;
171}
172
174static inline volatile r_port_regs_t* ra8_port1(void)
175{
176 return (volatile r_port_regs_t*)k_ra8_port1_base_addr;
177}
178
180static inline volatile r_port_regs_t* ra8_port2(void)
181{
182 return (volatile r_port_regs_t*)k_ra8_port2_base_addr;
183}
184
186static inline volatile r_port_regs_t* ra8_port3(void)
187{
188 return (volatile r_port_regs_t*)k_ra8_port3_base_addr;
189}
190
192static inline volatile r_port_regs_t* ra8_port4(void)
193{
194 return (volatile r_port_regs_t*)k_ra8_port4_base_addr;
195}
196
198static inline volatile r_port_regs_t* ra8_port5(void)
199{
200 return (volatile r_port_regs_t*)k_ra8_port5_base_addr;
201}
202
204static inline volatile r_port_regs_t* ra8_port6(void)
205{
206 return (volatile r_port_regs_t*)k_ra8_port6_base_addr;
207}
208
210static inline volatile r_port_regs_t* ra8_port7(void)
211{
212 return (volatile r_port_regs_t*)k_ra8_port7_base_addr;
213}
214
216static inline volatile r_port_regs_t* ra8_port8(void)
217{
218 return (volatile r_port_regs_t*)k_ra8_port8_base_addr;
219}
220
222static inline volatile r_port_regs_t* ra8_port9(void)
223{
224 return (volatile r_port_regs_t*)k_ra8_port9_base_addr;
225}
226
228static inline volatile r_port_regs_t* ra8_port10(void)
229{
230 return (volatile r_port_regs_t*)k_ra8_port10_base_addr;
231}
232
234static inline volatile r_port_regs_t* ra8_port11(void)
235{
236 return (volatile r_port_regs_t*)k_ra8_port11_base_addr;
237}
238
240static inline volatile r_port_regs_t* ra8_port12(void)
241{
242 return (volatile r_port_regs_t*)k_ra8_port12_base_addr;
243}
244
246static inline volatile r_port_regs_t* ra8_port13(void)
247{
248 return (volatile r_port_regs_t*)k_ra8_port13_base_addr;
249}
250
252static inline volatile r_port_regs_t* ra8_port14(void)
253{
254 return (volatile r_port_regs_t*)k_ra8_port14_base_addr;
255}
256
257/* =============================================================================
258 * Bit-helper enums for PCNTR1/2/3/4 halves
259 * =============================================================================
260 */
261
270
271#ifdef __cplusplus
272}
273#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
Named Bit Positions and Masks for Register Manipulation.
Typed Port / Pin Constants for the RA8D2 IOPORT Module.
ra8_port_t
Port indices for the RA8D2 IOPORT module.
@ k_ra8_port_max
Highest valid port index.
static volatile r_port_regs_t * ra8_port4(void)
Get PORT4 registers.
ra8_pcntr_half_t
Bit shifts for the halves inside each PCNTR register.
@ k_ra8_pcntr_low_half_shift
PDR/PIDR/POSR/EOSR half.
@ k_ra8_pcntr_high_half_shift
PODR/EIDR/PORR/EORR half.
static volatile r_port_regs_t * ra8_port14(void)
Get PORT14 registers.
static volatile r_port_regs_t * ra8_port10(void)
Get PORT10 registers.
static volatile r_port_regs_t * ra8_port12(void)
Get PORT12 registers.
static volatile r_port_regs_t * ra8_port13(void)
Get PORT13 registers.
static volatile r_port_regs_t * ra8_port11(void)
Get PORT11 registers.
static volatile r_port_regs_t * ra8_port1(void)
Get PORT1 registers.
static volatile r_port_regs_t * ra8_port8(void)
Get PORT8 registers.
ra8_port_regs_size_t
Expected byte size of the per-port register window.
@ k_ra8_port_regs_bytes
RA8 port registers bytes.
static volatile r_port_regs_t * ra8_port3(void)
Get PORT3 registers.
static volatile r_port_regs_t * ra8_port0(void)
Get PORT0 registers.
static volatile r_port_regs_t * ra8_port5(void)
Get PORT5 registers.
static volatile r_port_regs_t * ra8_port9(void)
Get PORT9 registers.
static volatile r_port_regs_t * ra8_port(ra8_port_t port)
Get the PORT register window for a given port index.
static volatile r_port_regs_t * ra8_port6(void)
Get PORT6 registers.
static volatile r_port_regs_t * ra8_port2(void)
Get PORT2 registers.
ra8_port_addr_t
@ k_ra8_port0_base_addr
RA8 port0 base address.
@ k_ra8_port4_base_addr
RA8 port4 base address.
@ k_ra8_port_stride
Bytes between adjacent ports.
@ k_ra8_port5_base_addr
RA8 port5 base address.
@ k_ra8_port9_base_addr
RA8 port9 base address.
@ k_ra8_port8_base_addr
RA8 port8 base address.
@ k_ra8_port12_base_addr
RA8 port12 base address.
@ k_ra8_port11_base_addr
RA8 port11 base address.
@ k_ra8_port7_base_addr
RA8 port7 base address.
@ k_ra8_port3_base_addr
RA8 port3 base address.
@ k_ra8_port2_base_addr
RA8 port2 base address.
@ k_ra8_port14_base_addr
RA8 port14 base address.
@ k_ra8_port1_base_addr
RA8 port1 base address.
@ k_ra8_port13_base_addr
RA8 port13 base address.
@ k_ra8_port10_base_addr
RA8 port10 base address.
@ k_ra8_port6_base_addr
RA8 port6 base address.
static volatile r_port_regs_t * ra8_port7(void)
Get PORT7 registers.
Per-port IOPORT register window.
volatile uint32_t PCNTR2
PCNTR2 – { EIDR[31:16], PIDR[15:0] } (read-only).
volatile uint32_t PCNTR3
PCNTR3 – { PORR[31:16], POSR[15:0] } (write-only).
volatile uint32_t PCNTR1
PCNTR1 – { PODR[31:16], PDR[15:0] }.
volatile uint32_t PCNTR4
PCNTR4 – { EORR[31:16], EOSR[15:0] }.