ra8_usb_device.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_usb.h"
#include "ra8_usb_internal.h"
#include "ra8_usb_regs.h"
 
static const char* s_tag = "USB";
 
/* =============================================================================
 * Device-mode bring-up diagnostic probes (read via JLink)
 * =============================================================================
 */

volatile uint16_t g_syscfg_after_phy_bringup = 0U;

volatile uint16_t g_lpsts_after_phy_bringup = 0U;

volatile uint16_t g_syscfg_after_attach = 0U;

volatile uint16_t g_lpsts_after_attach = 0U;

volatile uint16_t g_syssts0_after_attach = 0U;

volatile uint16_t g_syscfg_before_dprpu = 0U;
 
/* =============================================================================
 * Device-mode state decode
 * =============================================================================
 */

RA8_INTERNAL
static ra8_usb_dev_state_t internal_decode_dvsq(uint16_t intsts0)
{
  const uint16_t dvsq = (uint16_t)(intsts0 & k_ra8_intsts0_mask_dvsq);
  /* Suspend bit (0x40) wins over the lower three states. */
  if ((dvsq & k_ra8_dvsq_suspend) != 0U) {
    return k_ra8_usb_dev_state_suspended;
  }
  if (dvsq == k_ra8_dvsq_default) {
    return k_ra8_usb_dev_state_default;
  }
  if (dvsq == k_ra8_dvsq_address) {
    return k_ra8_usb_dev_state_address;
  }
  if (dvsq == k_ra8_dvsq_configured) {
    return k_ra8_usb_dev_state_configured;
  }
  return k_ra8_usb_dev_state_powered;
}

ra8_err_t ra8_usb_device_init(ra8_usb_speed_t speed)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 11.2.7 "MSTPCRB : Module Stop Control Register B", p 444 */
  const ra8_err_t mst_err = ra8_mstp_enable(priv_mstp(speed));
  RA8_RETURN_ON_ERROR(mst_err, s_tag, "usb_init: mstp enable");
 
  if (speed == k_ra8_usb_speed_hs) {
    const ra8_err_t phy_err = priv_usbhs_phy_bringup(reg);
    /* GCOVR_EXCL_BR_START -- HW bring-up fault */
    RA8_RETURN_ON_ERROR(phy_err, s_tag, "usb_init: HS PHY bring-up");
    /* GCOVR_EXCL_BR_STOP */
  } else {
    const ra8_err_t fs_err = priv_usbfs_module_bringup(reg);
    RA8_RETURN_ON_ERROR(fs_err, s_tag, "usb_init: FS module bring-up");
  }
 
  priv_usb_init_common(reg);
 
  /* Bisect probes: capture SYSCFG/LPSTS state at the END of device-init,
   * BEFORE control returns to ra8_board_usbhs_device_init / the DCD
   * bridge. HUM Ch 37.2.1 SYSCFG p 2060, HUM Ch 37.2.43 LPSTS p 2111. */
  if (speed == k_ra8_usb_speed_hs) {
    g_syscfg_after_phy_bringup = reg->SYSCFG;
    g_lpsts_after_phy_bringup  = *ra8_usbhs_lpsts();
  }
 
  ra8_log_info_val(s_tag, "usb device init speed", (uint32_t)speed);
  return k_ra8_ok;
}

ra8_err_t ra8_usb_device_deinit(ra8_usb_speed_t speed)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 36.2.10 "INTENB0 : Interrupt Enable Register 0", p 1980 */
  reg->INTENB0 = 0U;
  reg->INTENB1 = 0U;
  reg->BRDYENB = 0U;
  reg->NRDYENB = 0U;
  reg->BEMPENB = 0U;
 
  /* HUM Ch 36.2.1 "SYSCFG : System Configuration Control Register", p 1967 */
  reg->SYSCFG = 0U;
  return ra8_mstp_disable(priv_mstp(speed));
}

ra8_err_t ra8_usb_device_attach(ra8_usb_speed_t speed, bool attached)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 36.2.1 "SYSCFG : System Configuration Control Register", p 1967 */
  /* HUM Ch 37.2.1 "SYSCFG : System Configuration Control Register", p 2061 */
  const uint16_t dprpu = (uint16_t)(1U << k_ra8_syscfg_bit_dprpu);
  const uint16_t cnen  = (uint16_t)(1U << k_ra8_syscfg_bit_cnen);
 
  if (attached) {
    /* HUM Ch 37.2.1 SYSCFG, "CNEN bit (Single-ended Receiver Enable)"
     * p 2062: "In device controller mode, set this bit to 1 when VBUS
     * is detected because of a VBUS interrupt, and set it to 0 when
     * the VBUS line is removed."
     *
     * Without CNEN=1 the HS PHY's single-end receivers are powered
     * down and SYSSTS0.LNST[1:0] reads 00b (SE0) regardless of what
     * the host's 1.5 kohm-or-15 kohm pull-down arrangement and the
     * device's DPRPU 1.5 kohm pull-up are doing on the wires.
     *
     * Programme CNEN BEFORE DPRPU so the receivers latch the line
     * state the moment DPRPU pulls D+ high; this is the FS-attach
     * sequence sketched in HUM Ch 37.3.3 Figure 37.2 p 2121
     * ("Resistor control" step comes after USBE/CNEN are settled).
     * The FS instance has no CNEN gate (HUM Ch 36.2.1 SYSCFG p 1966),
     * so CNEN is HS-only here. */
    if (speed == k_ra8_usb_speed_hs) {
      priv_rmw16(&reg->SYSCFG, cnen, 0U);
      g_syscfg_before_dprpu = reg->SYSCFG;
    }
    priv_rmw16(&reg->SYSCFG, dprpu, 0U);
  } else {
    priv_rmw16(&reg->SYSCFG, 0U, dprpu);
    if (speed == k_ra8_usb_speed_hs) {
      /* HUM Ch 37.2.1 p 2062: clear CNEN when VBUS is removed /
       * detach is requested, to avoid through-current on floating
       * D+/D- when the cable is unplugged. */
      priv_rmw16(&reg->SYSCFG, 0U, cnen);
    }
  }
 
  /* Bisect probes: capture SYSCFG/LPSTS/SYSSTS0 at end of attach. HUM
   * Ch 37.2.1 SYSCFG p 2060, HUM Ch 37.2.3 SYSSTS0 p 2063, HUM
   * Ch 37.2.43 LPSTS p 2111. */
  if (speed == k_ra8_usb_speed_hs) {
    g_syscfg_after_attach  = reg->SYSCFG;
    g_lpsts_after_attach   = *ra8_usbhs_lpsts();
    g_syssts0_after_attach = reg->SYSSTS0;
  }
  return k_ra8_ok;
}
 
/* =============================================================================
 * Status / state
 * =============================================================================
 */

ra8_err_t ra8_usb_get_status(ra8_usb_speed_t speed, uint16_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, s_tag, "out_mask must not be nullptr");
  volatile const r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 36.2.14 "INTSTS0 : Interrupt Status Register 0", p 1986 */
  *out_mask = reg->INTSTS0;
  return k_ra8_ok;
}

ra8_err_t ra8_usb_clear_status(ra8_usb_speed_t speed, uint16_t mask)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 36.2.14 "INTSTS0 : Interrupt Status Register 0", p 1986 */
  reg->INTSTS0 = (uint16_t)(reg->INTSTS0 & (uint16_t)~mask);
  return k_ra8_ok;
}

ra8_err_t ra8_usb_get_device_state(ra8_usb_speed_t speed, ra8_usb_dev_state_t* out_state)
{
  RA8_CHECK_NULL_PTR(out_state, s_tag, "out_state must not be nullptr");
  volatile const r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 36.2.14 "INTSTS0 : Interrupt Status Register 0", p 1986 */
  *out_state = internal_decode_dvsq(reg->INTSTS0);
  return k_ra8_ok;
}

ra8_err_t ra8_usb_set_address(ra8_usb_speed_t speed, uint8_t address)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (address > k_ra8_usb_max_address) {
    return k_ra8_err_invalid_arg;
  }
  /* HUM Ch 36.2.16 "USBADDR : USB Address Register", p 1994 */
  /* HUM Ch 37.2.16 "USBADDR : USB Address Register", p 2089 */
  reg->USBADDR = (uint16_t)((uint16_t)address & k_ra8_usbaddr_addr_mask);
  return k_ra8_ok;
}

RA8_INTERNAL
static void internal_dcp_reset_defaults(volatile r_usb_regs_t* reg)
{
  reg->DCPCFG  = 0U;
  reg->DCPMAXP = k_ra8_usb_dcp_max_packet;
  priv_select_cfifo(reg, 0U, true);
  reg->CFIFOCTR = (uint16_t)k_ra8_fifoctr_bclr;
}

ra8_err_t ra8_usb_device_busreset_rearm(ra8_usb_speed_t speed)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 36.2.27 "PIPECTR : Pipe n Control Register", p 2007.
   * Clear PID for every non-control pipe so any half-completed pre-
   * reset transfer is forgotten. The class driver re-issues queue_in /
   * queue_out which will set PID=BUF when ready. */
  for (uint8_t i = 0U; i < (uint8_t)k_ra8_usb_pipectr_count; i++) {
    reg->PIPECTR[i] = 0U;
  }
 
  /* HUM Ch 36.2.13/14 BRDYSTS / NRDYSTS / BEMPSTS, p 1983-1985 (W0C).
   * Drop any per-pipe status bits left over from before the reset so
   * stale BRDY edges don't fire spurious BRDY callbacks during the next
   * enumeration. Writing 0 clears every bit; writing 1 preserves. */
  reg->BRDYSTS = 0U;
  reg->NRDYSTS = 0U;
  reg->BEMPSTS = 0U;
 
  /* DCP defaults + FIFO clear (see helper). HUM Ch 36.2.19 / 37.2.29
   * DCPCFG p 1989 / 2091 and HUM Ch 36.2.20 / 37.2.30 DCPMAXP p 1990
   * / 2092. DCPCTR is intentionally NOT written here: HUM Ch 36.2.21
   * / 37.2.31 (p 1991 / 2093) states the IP auto-defaults the
   * writable DCPCTR fields on bus reset (PID=NAK, CCPL=0). */
  internal_dcp_reset_defaults(reg);
 
  /* HUM Ch 36.2.10 "INTENB0 : Interrupt Enable Register 0", p 1980.
   * Some RA silicon revisions clear individual INTENB0 bits across a
   * bus reset (notably CTRT). Re-apply the post-init mask defensively
   * so the next SETUP raises CTRT as expected. Mirrors the mask in
   * priv_usb_init_common. */
  /* SOFR and RSME are intentionally NOT enabled here:
   *   - SOFR fires every 125us on HS (= 8 kHz);
   *   - RSME stays asserted on USBHS via the PHY's USBR signal
   *     while the host holds the bus in resume signalling;
   * Both starve PendSV and the demo worker thread never gets
   * scheduled. NRDY is still useful (drives the bridge's per-pipe
   * NAK re-arm) and does not cause a storm on its own. RSME / SOFR
   * status is still readable from INTSTS0 for poll-style drivers. */
  reg->INTENB0 = (uint16_t)((1U << k_ra8_int0_bit_bemp) | (1U << k_ra8_int0_bit_brdy) |
                            (1U << k_ra8_int0_bit_nrdy) | (1U << k_ra8_int0_bit_ctrt) |
                            (1U << k_ra8_int0_bit_dvst) | (1U << k_ra8_int0_bit_vbse));
 
  return k_ra8_ok;
}
/* =============================================================================
 * Endpoints
 * =============================================================================
 */

RA8_INTERNAL
static ra8_err_t internal_check_ep_args(uint8_t           pipe_num,
                                        uint8_t           ep_addr,
                                        ra8_usb_ep_dir_t  dir,
                                        ra8_usb_ep_type_t type,
                                        uint16_t          max_packet)
{
  if ((pipe_num == 0U) || (pipe_num > k_ra8_usb_max_pipe_num)) {
    return k_ra8_err_invalid_arg;
  }
  if ((ep_addr == 0U) || (ep_addr > k_ra8_usb_max_ep_addr)) {
    return k_ra8_err_invalid_arg;
  }
  if ((dir != k_ra8_usb_ep_dir_in) && (dir != k_ra8_usb_ep_dir_out)) {
    return k_ra8_err_invalid_arg;
  }
  if (type > k_ra8_usb_ep_type_iso) {
    return k_ra8_err_invalid_arg;
  }
  if ((max_packet == 0U) || (max_packet > k_ra8_usb_pipe_max_packet)) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL
static void
internal_pipe_finalize(volatile r_usb_regs_t* reg, uint8_t pipe_num, ra8_usb_ep_dir_t dir)
{
  const uint8_t  ctr_idx  = (uint8_t)(pipe_num - 1U);
  const uint16_t pipe_bit = (uint16_t)(1U << pipe_num);
  priv_rmw16(&reg->PIPECTR[ctr_idx], k_ra8_pipectr_sqclr, 0U);
  priv_rmw16(&reg->PIPECTR[ctr_idx], k_ra8_pipectr_aclrm, 0U);
  priv_rmw16(&reg->PIPECTR[ctr_idx], 0U, k_ra8_pipectr_aclrm);
  reg->BRDYSTS = (uint16_t)(~pipe_bit);
  reg->BEMPSTS = (uint16_t)(~pipe_bit);
  priv_pipe_pid(reg, pipe_num, (dir == k_ra8_usb_ep_dir_out) ? k_ra8_pid_buf : k_ra8_pid_nak);
}

RA8_INTERNAL
static void
internal_pipe_arm_irq(volatile r_usb_regs_t* reg, uint8_t pipe_num, ra8_usb_ep_dir_t dir)
{
  const uint16_t pipe_bit = (uint16_t)(1U << pipe_num);
  if (dir == k_ra8_usb_ep_dir_out) {
    reg->BRDYENB = (uint16_t)(reg->BRDYENB | pipe_bit);
  } else {
    reg->BEMPENB = (uint16_t)(reg->BEMPENB | pipe_bit);
  }
}

ra8_err_t ra8_usb_configure_endpoint(ra8_usb_speed_t   speed,
                                     uint8_t           pipe_num,
                                     uint8_t           ep_addr,
                                     ra8_usb_ep_dir_t  dir,
                                     ra8_usb_ep_type_t type,
                                     uint16_t          max_packet)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  const ra8_err_t arg_err = internal_check_ep_args(pipe_num, ep_addr, dir, type, max_packet);
  if (arg_err != k_ra8_ok) {
    return arg_err;
  }
 
  priv_pipe_quiesce(reg, pipe_num);
 
  /* HUM Ch 36.2.23 "PIPESEL : Pipe Window Select Register", p 2002 */
  reg->PIPESEL = pipe_num;
  /* HUM Ch 36.2.24 "PIPECFG : Pipe Configuration Register", p 2003 */
  reg->PIPECFG = priv_pipecfg_word(ep_addr, dir, type, false);
  /* HUM Ch 37.2.35 "PIPEBUF : Pipe Buffer Register", p 2100. PIPEBUF is a
   * USBHS-only register; the USBFS instance (Ch 36) has no equivalent.
   * Bulk pipes get a single MPS-sized bank (DBLB clear). Interrupt/iso
   * pipes keep the reset default. */
  if (type == k_ra8_usb_ep_type_bulk) {
    reg->PIPEBUF = priv_pipebuf_word(pipe_num, max_packet);
  }
  /* HUM Ch 36.2.26 "PIPEMAXP : Pipe Maximum Packet Size Register", p 2005 */
  reg->PIPEMAXP = max_packet;
  reg->PIPEPERI = 0U;
  /* Deselect window (FIT step 4) so a later stray PIPECFG write does
   * not land on this pipe. */
  reg->PIPESEL = 0U;
 
  internal_pipe_finalize(reg, pipe_num, dir);
  internal_pipe_arm_irq(reg, pipe_num, dir);
  return k_ra8_ok;
}

ra8_err_t ra8_usb_stall_endpoint(ra8_usb_speed_t speed, uint8_t pipe_num)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num > k_ra8_usb_max_pipe_num) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num == 0U) {
    /* HUM Ch 36.2.21 "DCPCTR : DCP Control Register", p 1999 */
    priv_dcp_pid(reg, k_ra8_pid_stall);
  } else {
    /* HUM Ch 36.2.27 "PIPEnCTR : PIPE n Control Register", p 2005 */
    priv_pipe_pid(reg, pipe_num, k_ra8_pid_stall);
  }
  return k_ra8_ok;
}