58typedef enum : uint16_t {
70typedef enum : uint16_t {
76typedef enum : uint16_t {
85typedef enum : uint32_t {
93typedef enum : uint16_t {
155RA8_PRIV void priv_rmw16(
volatile uint16_t* reg, uint16_t set_mask, uint16_t clr_mask);
Annotation-attribute framework macros for ra8-firmware.
#define RA8_PRIV
Module-private helper: shared across TUs but only inside one library.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Ref-counted Module Stop Control wrapper for the RA8D2.
ra8_mstp_t
Packed (reg << 8) | bit module-stop identifier.
Native USB controller driver public API (device + host modes).
ra8_usb_ep_type_t
Transfer type for a non-control endpoint.
ra8_usb_ep_dir_t
Endpoint direction.
ra8_usb_speed_t
Selects which controller instance the call targets.
void priv_fifo_write(volatile r_usb_regs_t *reg, const uint8_t *data, uint16_t len)
Push a byte buffer into the CFIFO data port.
void priv_dcp_pid(volatile r_usb_regs_t *reg, ra8_usb_pid_t pid)
Set DCPCTR PID field while preserving the rest of the register.
void priv_rmw16(volatile uint16_t *reg, uint16_t set_mask, uint16_t clr_mask)
Apply a generic read-modify-write to a 16-bit register.
void priv_select_cfifo(volatile r_usb_regs_t *reg, uint16_t pipe_num, bool is_in_dir)
Set CFIFOSEL.MBW + CURPIPE + ISEL for the given pipe / direction.
ra8_err_t priv_wait_frdy(volatile r_usb_regs_t *reg)
Spin until CFIFOCTR.FRDY asserts or a deadline elapses.
ra8_usb_host_devadd_t
Offsets / shifts for the device-address (DEVADDn) registers.
@ k_ra8_usb_devadd0_off
DEVADD0 byte offset from base.
@ k_ra8_usb_dev_addr_max
Highest DEVADDn slot (DEVADDA).
@ k_ra8_usb_usbspd_shift
DEVADDn.USBSPD field position.
@ k_ra8_usb_devadd_stride
Bytes between DEVADDn slots.
ra8_mstp_t priv_mstp(ra8_usb_speed_t speed)
Resolve the per-speed MSTP id.
volatile r_usb_regs_t * priv_pick(ra8_usb_speed_t speed)
Resolve the per-speed register pointer.
bool priv_is_hs(volatile const r_usb_regs_t *reg)
Detect whether reg points at the USBHS (IP1) register block.
ra8_err_t priv_usbhs_phy_bringup(volatile r_usb_regs_t *reg)
USBHS embedded-PHY bring-up (HUM Figure 37.2 p 2121).
ra8_err_t priv_dcp_push_chunk(volatile r_usb_regs_t *reg, const uint8_t *p, uint16_t n)
Push a single DCP IN chunk: wait FRDY, write FIFO, pulse BVAL.
uint16_t priv_pipebuf_word(uint8_t pipe_num, uint16_t max_packet)
Compute the PIPEBUF word for a bulk pipe (2*MPS region).
void priv_host_program_devadd(volatile r_usb_regs_t *reg, uint8_t dev_addr)
Program DEVADDn.USBSPD with the connected device's link speed.
ra8_usb_byte_mask_t
Byte-extraction masks shared across the FIFO byte path.
@ k_ra8_usb_byte_mask
Low byte of a 16-bit FIFO word.
@ k_ra8_usb_byte_bits
Bits per byte (shift constant).
ra8_usb_host_addr_bits_t
Field layout helpers for host-mode device addressing.
@ k_ra8_usb_devsel_shift
DCPMAXP/PIPEMAXP DEVSEL pos.
@ k_ra8_usb_devsel_field_mask
DEVSEL width once shifted.
@ k_ra8_usb_pid_stall_bit
PID[1]: set for either STALL.
@ k_ra8_usb_pipemaxp_mxps
PIPEMAXP MXPS field (the USBHS instance carries 11 bits, HUM Ch 37.2.36; FS uses the low 9).
void priv_pipe_pid(volatile r_usb_regs_t *reg, uint8_t pipe_num, ra8_usb_pid_t pid)
Set PIPECTR[idx] PID field.
void priv_usb_init_common(volatile r_usb_regs_t *reg)
Programme the post-SYSCFG common registers (FIFO, DCP, INTENB).
void priv_pipe_quiesce(volatile r_usb_regs_t *reg, uint8_t pipe_num)
Quiesce the pipe so PIPECFG/PIPEMAXP/PIPEPERI become writable.
void priv_fifo_read(volatile r_usb_regs_t *reg, uint8_t *data, uint16_t len)
Drain the CFIFO data port into a buffer.
uint16_t priv_pipecfg_word(uint8_t ep_addr, ra8_usb_ep_dir_t dir, ra8_usb_ep_type_t type, bool dblb_in)
Pack PIPECFG fields for a configured non-control pipe.
ra8_usb_internal_lim_t
Driver-wide bounds that aren't part of the public API.
@ k_ra8_usb_max_address
7-bit USB address.
@ k_ra8_usb_pipe_max_packet
Max packet ceiling for pipes.
@ k_ra8_usb_max_pipe_num
PIPE1..PIPE9 + DCP at 0.
@ k_ra8_usb_max_ep_addr
USB EP number is 4 bits.
@ k_ra8_usb_dcp_max_packet
EP0 default packet size.
ra8_usb_host_ctrl_bits_t
Bit masks used by the host control-transfer engine.
@ k_ra8_usb_dcpmaxp_mxps
DCPMAXP MXPS (max packet) field.
@ k_ra8_usb_rhst_mask
DVSTCTR0.RHST connected-speed.
@ k_ra8_usb_dcp_pipe0_bit
BRDYSTS/BEMPSTS DCP (pipe 0) bit.
@ k_ra8_usb_lnst_mask
SYSSTS0.LNST line-state field.
@ k_ra8_usb_setup_dir_in
bmRequestType device-to-host bit.
ra8_err_t priv_usbfs_module_bringup(volatile r_usb_regs_t *reg)
USBFS module bring-up (FSP hw_usb_pmodule_init IP0 branch).
USB Full-Speed + High-Speed controller layout for the Renesas RA8D2.
ra8_usb_pid_t
Response PID values written into the low two bits of DCPCTR / PIPECTR.
USB FS / HS register window (device-mode subset).